MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 328

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Clocks and Power Control
A write of 0x55CCAA33 to the associated key register changes the key to the open state. A write of any
other data to this location changes the key to the locked state. The key registers are write-only. A read of
the key register has undefined side effects and may be interpreted as a write that locks the associated
register.
Table 8-8
8-26
SPR Number
Address or
0x2F C22C
0x2F C200
0x2F C204
0x2F C208
0x2F C220
0x2F C224
0x2F C228
0x2F C240
0x2F C244
0x2F C280
0x2F C284
lists the registers powered by KAPWR and the associated key registers.
Time Base Status and Control (TBSCR)
See
Time Base Reference 0 (TBREF0)
See
Reference Registers (TBREF0 and
TBREF1)” for bit descriptions.
Time Base Reference 1 (TBREF1)
See
Reference Registers (TBREF0 and
TBREF1)
(RTCSC)
See
register is locked after reset by default.
See
Register
register is locked after reset by default.
Reserved. This register is locked after
reset by default.
See
Alarm Register
descriptions. This register is locked after
reset by default.
See
See
See
Register (PLPRCR)
See
Real Time Clock Status and Control
Real Time Clock (RTC)
Real Time Alarm Seconds (RTSEC)
Real Time Alarm (RTCAL)
PIT Status and Control (PISCR)
PIT Count (PITC)
System Clock Control Register (SCCR)
PLL Low-Power and Reset-Control
KAPWR Register
Table 6-18
Section 6.2.2.4.3, “Time Base
Section 6.2.2.4.3, “Time Base
Table 6-19
Section 6.2.2.4.6, “Real-Time Clock
Section 6.2.2.4.7, “Real-Time Clock
Table 6-20
Table 6-21
Table 8-9
Table 8-11
(RTC)” for bit descriptions. This
for bit descriptions.
Table 8-8. KAPWR Registers and Key Registers
for bit descriptions.
(RTCAL)” for bit
for bit descriptions.
for bit descriptions. This
for bit descriptions.
for bit descriptions.
for bit descriptions.
Register
MPC561/MPC563 Reference Manual, Rev. 1.2
0x2F C32C Real Time Alarm Key (RTCALK)
0x2F C300
0x2F C304
0x2F C308
0x2F C320
0x2F C324
0x2F C328
0x2F C340
0x2F C344
0x2F C380
0x2F C384
Address
Time Base Status and Control Key
(TBSCRK)
Time Base Reference 0 Key (TBREF0K)
Time Base Reference 1 Key (TBREF1K)
Real Time Clock Status and Control Key
(RTCSCK)
Real Time Clock Key (RTCK)
Real Time Alarm Seconds Key (RTSECK)
PIT Status and Control Key (PISCRK)
PIT Count Key (PITCK)
System Clock Control Key (SCCRK)
PLL Low-Power and Reset-Control
Register Key (PLPRCRK)
Associated Key Register
Register
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