MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 865

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

To prevent unnecessary page accesses from the array, the UC3F memory interface (MI) monitors the
incoming address to determine if the required information is in one of the two read page buffers. This
strategy allows the UC3F array to have an off page access and an on page access. In normal operation,
write accesses to the UC3F array are not recognized except during program and erase operations.
The UC3F EEPROM uses an embedded hardware algorithm to program and erase the UC3F array. Special
control logic is included to guard against accidental program or erase by requiring a specific series of read
and write accesses to the UC3F control registers. External inputs provide a hardware protection
mechanism to prevent accidental program and erase of UC3F array blocks. The hardware algorithm
automatically performs all necessary applications of high voltage pulses and verify reads of the UC3F
array to ensure that all bits are programmed and erased with sufficient margin to guarantee data integrity
and reliability.
21.0.1
Freescale Semiconductor
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High density single transistor Flash bit cell
-40 to 125° C ambient temperature operating range
— -40 to 85° C on the suffix C device
2.5-V to 2.7-V V
Shadow information stored in special Flash NVM shadow locations
512 Kbytes using 64-Kbyte blocks
— Two 16-Kbyte small blocks
Array block restriction control for small and large blocks
— Erase by array blocks
— Array protection for program and erase operations
— Array block assignment of supervisor or supervisor/user space
— Array block assignment of data or instruction/data space
Internal 64-bit data path architecture
Page mode read
— Retains two independent read page buffers
— Read page size of 32 bytes (8 words).
Word (32-bit) programming
Embedded hardware program and erase algorithm
— Uses internal oscillator to time program and erase pulses. Pulses are timed independently of
— Automatically performs margin reads
External Flash program or erase enable inputs for block 0 or entire Flash array (B0EPEE and
EPEE)
Low power disable via an external signal or UC3F register bit
Censor mode for Flash memory array access restriction with a user bypass for unrestricted array
access
system clock frequency
Features of the CDR3 Flash EEPROM (UC3F)
DDF
operating range and 4.75-V to 5.25-V V
MPC561/MPC563 Reference Manual, Rev. 1.2
FLASH
operating range
CDR3 Flash (UC3F) EEPROM
21-3