MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 188

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Central Processing Unit
3.14.5
When executing an eieio instruction, the load/store unit will wait until all previous accesses have
terminated before issuing cycles associated with load/store instructions following the eieio instruction.
3.14.6
A description of the time base register may be found in
and in
3.15
The MPC561/MPC563 has an internal memory space that includes memory-mapped control registers and
internal memory used by various modules on the chip. This memory is part of the main memory as seen
by the RCPU and can be accessed by an external system master.
3.15.1
3.15.1.1
The floating-point exception mode encoding in the RCPU is as shown in
The SF bit is reserved set to zero. The IP bit initial state after reset is set as programmed by the reset
configuration as specified by the USIU characteristics.
3.15.1.2
The RCPU implements all the instructions defined for the branch processor in the UISA in the hardware.
3.15.2
3.15.2.1
3-44
:
•
•
Chapter 8, “Clocks and Power
Unsupported Registers — The following registers are not supported by the MPC561/MPC563:
SDR, EAR, IBAT0U, IBAT0L, IBAT1U, IBAT1L, IBAT2U, IBAT2L, IBAT3U, IBAT3L,
DBAT0U, DBAT0L, DBAT1U, DBAT1L, DBAT2L, DBAT3U, DBAT3L.
Added Registers — For a list of added special purpose registers, refer to
Operating Environment Architecture (OEA)
Enforce In-Order Execution of I/O (eieio) Instruction
Time Base
Branch Processor Registers
Fixed-Point Processor
Machine State Register (MSR)
Branch Processors Instructions
Special Purpose Registers
Ignore exceptions
Precise
Precise
Precise
Table 3-21. Floating-Point Exception Mode Encoding
MPC561/MPC563 Reference Manual, Rev. 1.2
Mode
Control.”
Chapter 6, “System Configuration and
FE0
0
0
1
1
Table
FE1
0
1
0
1
3-21.
Table
Freescale Semiconductor
3-2, and
Protection,”
Table
3-3.