MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 962

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC561MZP56

Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant

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Development Support
Note: LCTRL1 is cleared following reset.
23.6.10 L-Bus Support Control Register 2
23-48
SRESET
SRESET
16:17
18:19
22:25
26:29
30:31
Field LW0EN
Field
Addr
Bits
20
21
LADC
LW1
MSB
16
0
Mnemonic
CGBMSK
CHBMSK
LW1LD
SUSG
SUSH
17
LW0IA
1
CSG
CSH
18
Figure 23-23. L-Bus Support Control Register 2 (LCTRL2)
2
LDDC
IADC
Table 23-24. LCTRL1 Bit Descriptions (continued)
LW0
LW1
19
3
Signed/unsigned operating mode
Signed/unsigned operating mode
Byte mask for 1st L-data comparator 0000 all bytes are not masked
Reserved
Compare size, comparator G
Compare size, comparator H
for comparator G
for comparator H
Byte mask for 2nd L-data
comparator
MPC561/MPC563 Reference Manual, Rev. 1.2
NOMSK
BRK
20
LW0LA
4
Description
21
5
LADC
LW0
0000_0000_0000_0000
0000_0000_0000_0000
22
6
SPR 157
23
7
LW0LD
24
8
00 reserved
01 word
10 half word
11 byte
(Must be programmed to word for floating point
compares)
0 unsigned
1 signed
(Must be programmed to signed for floating
point compares)
0001 the last byte of the word is masked
.
.
.
1111 all bytes are masked
LDDC
LW0
25
9
LW1
EN
10
26
11
27
LW1IA
Function
DLW0
EN
12
28
Freescale Semiconductor
DLW1
IADC
LW1
EN
13
29
SLW0
EN
14
30
LW1LA
SLW1
LSB
EN
15
31

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