MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 10

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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8.4.1.19
8.4.1.20
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8.4.1.40
8.4.1.41
8.4.1.42
8.4.1.43
8.5
8.5.1
8.5.1.1
8.5.2
8.5.3
8.5.4
8.5.4.1
8.5.5
8.5.6
8.5.7
8.5.8
8.5.8.1
8.5.8.2
8.5.8.2.1
8.5.9
8.5.10
x
Functional Description................................................................................................... 8-60
DDR SDRAM Interface Operation............................................................................ 8-64
DDR SDRAM Address Multiplexing........................................................................ 8-66
JEDEC Standard DDR SDRAM Interface Commands ............................................. 8-71
DDR SDRAM Interface Timing................................................................................ 8-72
DDR SDRAM Mode-Set Command Timing............................................................. 8-76
DDR SDRAM Registered DIMM Mode ................................................................... 8-77
DDR SDRAM Write Timing Adjustments ................................................................ 8-78
DDR SDRAM Refresh .............................................................................................. 8-79
DDR Data Beat Ordering........................................................................................... 8-83
Page Mode and Logical Bank Retention ................................................................... 8-83
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
DDR SDRAM Timing Configuration 5 (TIMING_CFG_5)................................. 8-37
DDR ZQ Calibration Control (DDR_ZQ_CNTL) ................................................ 8-39
DDR Write Leveling Control (DDR_WRLVL_CNTL) ........................................ 8-40
DDR Self Refresh Counter (DDR_SR_CNTR) .................................................... 8-43
DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1).................... 8-44
DDR SDRAM Register Control Word 2 (DDR_SDRAM_RCW_2).................... 8-45
DDR Debug Status Register 1 (DDRDSR_1) ....................................................... 8-46
DDR Debug Status Register 2 (DDRDSR_2) ....................................................... 8-47
DDR Control Driver Register 1 (DDRCDR_1)..................................................... 8-47
DDR Control Driver Register 2 (DDRCDR_2)..................................................... 8-50
DDR IP Block Revision 1 (DDR_IP_REV1)........................................................ 8-50
DDR IP Block Revision 2 (DDR_IP_REV2)........................................................ 8-51
Memory Data Path Error Injection Mask High (DATA_ERR_INJECT_HI) ........ 8-51
Memory Data Path Error Injection Mask Low (DATA_ERR_INJECT_LO)........ 8-52
Memory Data Path Error Injection Mask ECC (ERR_INJECT)........................... 8-52
Memory Data Path Read Capture High (CAPTURE_DATA_HI)......................... 8-53
Memory Data Path Read Capture Low (CAPTURE_DATA_LO) ........................ 8-54
Memory Data Path Read Capture ECC (CAPTURE_ECC).................................. 8-54
Memory Error Detect (ERR_DETECT)................................................................ 8-54
Memory Error Disable (ERR_DISABLE)............................................................. 8-56
Memory Error Interrupt Enable (ERR_INT_EN).................................................. 8-57
Memory Error Attributes Capture (CAPTURE_ATTRIBUTES).......................... 8-58
Memory Error Address Capture (CAPTURE_ADDRESS) .................................. 8-58
Memory Error Extended Address Capture (CAPTURE_EXT_ADDRESS)......... 8-59
Single-Bit ECC Memory Error Management (ERR_SBE) ................................... 8-59
Supported DDR SDRAM Organizations............................................................... 8-64
Clock Distribution ................................................................................................. 8-76
DDR SDRAM Refresh Timing.............................................................................. 8-80
DDR SDRAM Refresh and Power-Saving Modes ................................................ 8-80
Self-Refresh in Sleep Mode............................................................................... 8-82
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