MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 332

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
8.4.1.40
The memory error attributes capture register, shown in
type, size, source, and others.
Table 8-46
8.4.1.41
The memory error address capture register, shown in
a DDR ECC error is detected.
8-58
16–17
18–19
20–30
8–10
Bits
1–3
5–7
31
Offset 0xE4C
Reset
0
4
W
R
Offset 0xE50
Reset
BNUM Data beat number. Captures the doubleword number for the detected error. Relevant only for ECC errors.
Name
TTYP Transaction type for the error.
—
TSIZ
0
VLD
W
—
—
—
—
—
R
describes the CAPTURE_ATTRIBUTES fields.
1
Figure 8-41. Memory Error Attributes Capture Register (CAPTURE_ATTRIBUTES)
0
Memory Error Attributes Capture (CAPTURE_ATTRIBUTES)
Memory Error Address Capture (CAPTURE_ADDRESS)
BNUM
Figure 8-42. Memory Error Address Capture Register (CAPTURE_ADDRESS)
Reserved
Reserved
Transaction size for the error. Captures the transaction size in double words.
000 4 double words
001 1 double word
010 2 double words
011 3 double words
Others Reserved
Reserved
Reserved
00 Reserved
01 Write
10 Read
11 Read-modify-write
Reserved
Valid. Set as soon as valid information is captured in the error capture registers.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
3
—
4
Table 8-46. CAPTURE_ATTRIBUTES Field Descriptions
5
TSIZ
7
8
—
10 11
TSRC
All zeros
All zeros
CADDR
Figure
15 16 17 18 19 20
Description
Figure
—
8-42, holds the 32 lsbs of a transaction when
8-41, sets attributes for errors including
TTYP
Access: Read/Write
—
Freescale Semiconductor
Access: Read/Write
30
31
VLD
31