MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 85

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table
Number
8-59
8-60
8-61
8-62
8-63
8-64
8-65
8-66
8-67
8-68
8-69
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
9-19
9-20
9-21
9-22
9-23
9-24
9-25
9-26
9-27
9-28
9-29
Freescale Semiconductor
DDR2 Address Multiplexing with Partial Array Self Refresh Enabled ............................... 8-70
Example of Address Multiplexing for 64-bit Data Bus Interleaving Between
DDR SDRAM Command Table............................................................................................ 8-72
DDR SDRAM Interface Timing Intervals ............................................................................ 8-73
DDR SDRAM Power-Saving Modes Refresh Configuration............................................... 8-81
Memory Controller–Data Beat Ordering .............................................................................. 8-83
DDR SDRAM ECC Syndrome Encoding ............................................................................ 8-84
DDR SDRAM ECC Syndrome Encoding (Check Bits) ....................................................... 8-86
Memory Controller Errors .................................................................................................... 8-87
Memory Interface Configuration Register Initialization Parameters.................................... 8-87
Programming Differences Between Memory Types............................................................. 8-89
Processor Interrupts Generated Outside the Core—Types and Sources ................................. 9-4
Internal Interrupt Assignments................................................................................................ 9-6
Interrupt Signals—Detailed Signal Descriptions .................................................................... 9-8
PIC Register Address Map...................................................................................................... 9-9
BRR1 Field Descriptions ...................................................................................................... 9-19
BRR2 Field Descriptions ...................................................................................................... 9-20
FRR Field Descriptions......................................................................................................... 9-20
GCR Field Descriptions ........................................................................................................ 9-21
VIR Field Descriptions ......................................................................................................... 9-21
PIR Field Descriptions .......................................................................................................... 9-22
IPIVPRn Field Descriptions.................................................................................................. 9-23
SVR Field Descriptions ........................................................................................................ 9-23
TFRRx Field Descriptions .................................................................................................... 9-24
GTCCRxn Field Descriptions ............................................................................................... 9-24
GTBCRxn Field Descriptions ............................................................................................... 9-25
GTVPRxn Field Descriptions................................................................................................ 9-26
GTDRxn Field Descriptions .................................................................................................. 9-26
Parameters for Hourly Interrupt Timer Cascade Example.................................................... 9-27
TCRx Field Descriptions....................................................................................................... 9-28
ERQSR Field Descriptions ................................................................................................... 9-29
IRQSR0 Field Descriptions .................................................................................................. 9-30
IRQSR1 Field Descriptions .................................................................................................. 9-30
IRQSR2 Field Descriptions .................................................................................................. 9-31
CISR0 Field Descriptions ..................................................................................................... 9-31
CISR1 Field Descriptions ..................................................................................................... 9-32
CISR2 Field Descriptions ..................................................................................................... 9-32
PMnMR0 Field Descriptions ................................................................................................ 9-33
PMnMR1 Field Descriptions ................................................................................................ 9-34
PMnMR2 Field Descriptions ................................................................................................ 9-34
Two Banks with Partial Array Self Refresh Enabled ....................................................... 8-70
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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