MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 145

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.3.1
When the local e500 processor is used to configure CCSR space, the CCSR memory space should typically
be marked as cache-inhibited and guarded.
In addition, many configuration registers affect accesses to other memory regions; therefore writes to these
registers must be guaranteed to have taken effect before accesses are made to associated memory regions.
To guarantee that the results of any sequence of writes to configuration registers are in effect, the final
configuration register write should be chased by a read of the same register, and that should be followed
by a SYNC instruction. Then accesses can safely be made to memory regions affected by the configuration
register write.
2.3.2
In addition to being accessible by the e500 processor, the configuration, control, and status registers are
accessible from external interfaces, allowing external masters on the I/O ports to configure the MPC8536.
External masters do not need to know the location of the CCSR memory in the local address map. Rather, they
access this region of the local memory map through a window defined by a register in the interface
programming model that is accessible to the external master from its external memory map.
The PCI base address for accessing the local CCSR memory is selectable through the PCI configuration
and status register base address register (PCSRBAR), at offset 0x10, described in
Base Address Registers.”
to the MPC8536. Subsequent memory accesses by a PCI master to the PCI address range indicated by
PCSRBAR are translated to the local address indicated by the current setting of CCSRBAR.
2.3.3
The configuration, control, and status registers are grouped according to functional units. Most functional
blocks are allocated a 4-Kbyte address space for registers. Registers that fall into this category are referred
to as general utilities registers. These registers occupy the first 256 Kbytes of CCSR memory.
Registers controlling functions that are not particular to a functional unit but to the device as a whole occupy
the highest 256 Kbytes of CCSR memory and are referred to as device-specific registers.
Some functional units such as the OpenPIC-based interrupt controller have larger address spaces as
defined by their programming models. The registers for these blocks are given their own large regions of
CCSR memory.
Freescale Semiconductor
Accessing CCSR Memory from the Local Processor
Accessing CCSR Memory from External Masters
Organization of CCSR Memory
Table 2-10. Local Memory Configuration, Control, and Status Register Summary
Offset from CCSRBAR
0xC_0000–0xD_FFFF
0xE_0000–0xF_FFFF
0x8_0000–0xB_FFFF
0x0_0000–0x3_FFFF
0x4_0000–0x7_FFFF
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
An external PCI master sets this register by running a PCI configuration cycle
General utilities
Programmable interrupt controller (PIC)
Reserved
Reserved
Device-specific utilities
Register Grouping
Section 16.3.2.11, “PCI
Memory Map
2-11