MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1561

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 24-4
Table 24-4
16–20
21–25 BGRAN Burst granularity. The maximum number of clock cycles between events that are considered part of a single
26–31
Freescale Semiconductor
9–15
Bits
1–4
6–8
0
5
Offset 0xE_1020
Reset
W
R
EVENT Event selector. Up to 128 events selectable.
BDIST
BSIZE
Name
FC
CE
0xE_1030
0xE_1040
0xE_1050
0xE_1060
0xE_1070
0xE_1080
0xE_1090
0xE_10A0
0xE_10B0
0xE_10C0
FC
—
—
0
describes PMLCAn fields.
shows the performance monitor local control registers A1–A9.
Figure 24-4. Performance Monitor Local Control A Registers (PMLCA1–PMLCA9)
1
Freeze counter
0 The PMCs are incremented (if permitted by other PMC control bits).
1 The PMCs are not incremented (if permitted by other PMC control bits).
Reserved
Condition enable
0 Overflow conditions for PMC n cannot occur (PMC n cannot cause interrupts or freeze counters). Should be
1 Overflow conditions occur when PMC n [msb] is set.
Reserved
Note that with counter-specific events, an offset of 64 must be used when programming the field, because
counter-specific events occupy the bottom 64 values of the 7-bit event field where events are numbered. For
example, to specify counter-specific event 0, the event field must be programmed to 64.
See
Burst size. Fewest event occurrences that constitute a burst, that is, a rapid sequence of events followed by a
relatively long pause. A value less than two implies regular event counting. Any non-threshold, regular event
may be counted in a bursty fashion. See
burst. See
Burst distance (used with TBMULT). The number of clock cycles between bursts. Must be set to a value greater
than BSIZE for proper burstiness counting behavior.
00_0000 Regular counting
—
cleared when PMC n is used as a trigger or is selected for chaining.
Table 24-10
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
4
Section 24.4.6, “Burstiness Counting.”
CE
5
6
Table 24-4. PMLCA1–PMLCA9 Field Descriptions
for definition of events.
—
8
9
EVENT
Section 24.4.6, “Burstiness Counting,”
All zeros
15 16
Description
BSIZE
20 21
BGRAN
for more information.
Device Performance Monitor
25 26
Access: Read/Write
BDIST
24-7
31