MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 343

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13 x 10
13 x 10
Partial Array Self Refresh (PASR) can be enabled for any chip select using the
CSn_CONFIG_2[PASR_CFG] fields. If PASR is enabled for a given chip select, then the sub-bank and
row decode is swapped, and the sub-bank is decoded as the most significant portion of the DRAM address,
as shown in
interleaved chip select bit is placed immediately to the left of the column decode, as shown in
Freescale Semiconductor
x 3
x 2
x 3
x 2
x 3
x 2
14
10
14
10
13
10
13
10
x
x
x
x
Row
Row
Col
Col
x
MRAS 13
MCAS
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
x
MBA
MBA
MBA
MBA
MRAS
MCAS
MRAS
MCAS
MBA
MBA
Table 8-57. Example of Address Multiplexing for 64-Bit Data Bus Interleaving between
msb
msb
Table
4
4
Table 8-58. Example of Address Multiplexing for 64-Bit Data Bus Interleaving
12 11 10 9
13 12 11 10 9
12 11 10
5
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
8-59. If chip select interleaving and PASR are enabled for a chip select, then the
12 11 10 9
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
6
12 11 10 9
Two Banks with Partial Array Self Refresh Disabled (continued)
between Four Banks with Partial Array Self Refresh Disabled
7
12 11 10 9
8
9
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33–35
8
8
7
8
7
8
8
7
8
6
7
6
7
6
7
5
6
5
6
5
6
4
5
4
5
4
5
3
4
3
4
Address from Core Master
Address from Core Master
3
4
2
3
2
3
2
3
1
2
1
2
1
2
0
1 0
0
1
0
1
0
SEL
SEL
CS
CS
SEL
CS
0
SEL
SEL
CS
CS
SEL
2 1 0
2
CS
20 21 22 23 24 25 26 27 28 29 30 31 32 33–35
2
1 0
1
1
1
1
0
0
0
0
9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0
9
9
9
9
8
8
8
8
7
7
7
7
6
6
6
6
5
5
5
5
4
4
DDR Memory Controller
4
4
3
3
3
3
2
2
2
2
1
1
Table
1
1
0
0
0
0
8-60.
lsb
8-69
lsb