MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 440

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.1.4.4
The AFEU accelerates a bulk encryption algorithm compatible with the RC4 stream cipher from RSA
Security, Inc. The algorithm is byte-oriented, meaning the data to be ciphered can be any number of bytes.
The AFEU supports key lengths from 8 to 128 bits (in byte increments), providing a wide range of security
strengths.
For more information, refer to
10.1.4.5
The MDEU computes a single message digest (or hash or integrity check) value for all the data presented
on the input bus. The output size is determined by the specific algorithm, and is typically much smaller
than the input size.
The MDEU is designed to support the following hashing algorithms:
If a digest is supplied to the MDEU, it can do a bitwise check of this supplied digest against the one
computed by the MDEU (ICV checking).
For more information about the unit’s operation, refer to
(MDEU).”
10.1.4.6
The KEU (Kasumi Execution Unit) is a functional block capable of encrypting/decrypting and/or
performing integrity checks on 64-bit blocks of data using a 128-bit key. The KEU is designed support the
following cryptographic algorithms:
With the exception of f9, which is an authentication algorithm, KEU implements confidentiality
algorithms. For f9, if the KEU is supplied with a MAC value, it is capable of performing a bitwise check
of this original MAC against a f9 MAC generated by the KEU (ICV checking).
For more information about the unit’s operation, refer to
10.1.4.7
The CRCU computes a single 32-bit cyclic redundancy code (checksum) from all data presented on the
input bus.
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MD5 generates a 128-bit hash, and is specified in RFC 1321.
SHA-1 is a 160-bit hash function, specified by the NIST FIPS 180-1 standard.
SHA-224, SHA-256, SHA-384, and SHA-512 are 224-, 256-, 384-, and 512-bit hash functions
respectively, specified by the NIST FIPS 180-2 standard.
The MDEU also supports HMAC computations, as specified by the NIST FIPS-198 standard.
f8 and f9, as defined in the ETSI/SAGE Specification Document 1 for the 3GPP standard
A5/3 for GSM/EDGE
GEA3 for GPRS
Arc Four Execution Unit (AFEU)
Message Digest Execution Unit (MDEU)
Kasumi Execution Unit (KEU)
Cyclical Redundancy Check Unit (CRCU)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 10.7.2, “ARC4 Execution Unit (AFEU).”
Section 10.7.5, “Kasumi Execution Unit (KEU).”
Section 10.7.6, “Message Digest Execution Unit
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