MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1449

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.6.14.1.4 USB Interrupt (Interrupt on Completion (IOC))
Transfer Descriptors (iTDs, siTDs, and queue heads (qTDs)) contain a bit that can be set to cause an
interrupt on their completion. The completion of the transfer associated with that schedule item causes
USBSTS[UI] (USB interrupt) to be set. In addition, if a short packet is encountered on an IN transaction
associated with a queue head, then this event also causes USBINT to be set. If USBINTR[UE] (USB
interrupt enable) is set, a hardware interrupt is signaled to the system at the next interrupt threshold. If the
completion is because of errors, USBSTS[UEI] (USB error interrupt) is also set.
21.6.14.1.5 Short Packet
Reception of a data packet that is less than the endpoint's Max Packet size during Control, Bulk or Interrupt
transfers signals the completion of the transfer. Whenever a short packet completion occurs during a queue
head execution, USBSTS[UI] (USB interrupt bit) is set. If the USB interrupt enable bit is set
(USBINTR[UE]), a hardware interrupt is signaled to the system at the next interrupt threshold.
21.6.14.2 Host Controller Event Interrupts
These interrupt sources are independent of the interrupt threshold (with the one exception being the
Interrupt on Async Advance.
21.6.14.2.1 Port Change Events
Port registers contain status and status change bits. When the status change bits are set, the host controller
sets the USBSTS[PCI]. If the port change interrupt enable bit (PCE) in the USBINTR register is set, the
host controller issues a hardware interrupt. The port status change bits in PORTSC include:
21.6.14.2.2 Frame List Rollover
This event indicates that the host controller has wrapped the frame list. The current programmed size of
the frame list effects how often this interrupt occurs. If the frame list size is 1024, then the interrupt occurs
every 1024 milliseconds, if it is 512, then it occurs every 512 milliseconds, etc. When a frame list rollover
is detected, the host controller sets the frame list rollover bit, USBSTS[FRI]. If USBINTR[FRE] is set
(frame list rollover enable), the host controller issues a hardware interrupt. This interrupt is not delayed to
the next interrupt threshold.
21.6.14.2.3 Interrupt on Async Advance
This event is used for deterministic removal of queue heads from the asynchronous schedule. Whenever
the host controller advances the on-chip context of the asynchronous schedule, it evaluates the value of
USBCMD[IAA]. If it is set, it sets USBSTS[AAI]. If USBINTR[AAE] is set, the host controller issues a
hardware interrupt at the next interrupt threshold. A detailed explanation of this feature is described in
Section 21.6.9.2, “Removing Queue Heads from Asynchronous Schedule.”
Freescale Semiconductor
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Connect change status (CSC)
Port enable/disable change (PEC)
Over-current change (OCC)
Force port resume (FPR)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Universal Serial Bus Interfaces
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