MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 478

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.5.1.2.2
A detailed description for a system bus write with controller as master is as follows:
10.5.2
This section applies to both arbitration for use of the polychannel, and arbitration for use of execution
units. Control fields for both are in the master control register
(MCR)
In this section we refer to generic control fields CHN3_xx_PR_CNT and CHN4_xx_PR_CNT, where “xx”
refers to either “BUS” or “EU”.
If both CHN3_xx_PR_CNT and CHN4_xx_PR_CNT are zero (the default), the arbitration is round-robin
(see Section 10.5.2.1); otherwise a weighted priority scheme is used (see Section 10.5.2.2).
10.5.2.1
In round-robin arbitration, requesting channels are granted access in rotating numerical order: 1, 2, 3, 4, 1,
2, ... etc.
10.5.2.2
In the weighted priority scheme, the priority is as follows:
Initially, the priority is fixed from highest to lowest as channel 1, channel 2, channel 3, and channel 4, in
that order. When channel 3 has lost arbitration the number of times specified in CHN3_xx_PR_CNT,
channel 3 replaces channel 2 as the second-highest priority in the next round of arbitration. Likewise, when
channel 4 has lost arbitration the number of times specified in CHN4_xx_PR_CNT, channel 4 replaces
channel 2 as the second-highest priority in the next round of arbitration. These rules prevent channels 3
and 4 from being locked out.
10-48
1. Channel asserts its bus write request to the controller.
2. Channel furnishes internal read address, external write address, and transfer length.
3. Controller performs a read from the appropriate internal address supplied by the channel, loads the
4. When the system bus becomes available, controller writes data from its FIFO to the master
•
•
•
•
•
•
”)
write data into its FIFO, asserts a request to the system bus through the master interface, and waits
for the system bus to become available.
interface.
CHN3_BUS_PR_CNT and CHN4_BUS_PR_CNT control polychannel arbitration
CHN3_EU_PR_CNT and CHN4_EU_PR_CNT control EU arbitration
Channel 1—Highest priority
Channel 2—Second highest priority, unless CHN3_xx_PR_CNT or CHN4_xx_PR_CNT has
expired
Channel 3—Third priority, unless CHN4_xx_PR_CNT expired
Channel 4—Lowest priority, until CHN4_xx_PR_CNT expired
, as follows
Arbitration Algorithms
Round-Robin Arbitration
Weighted Priority Arbitration
System Bus Master Write—Detailed Description
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
:
(
Section 10.5.4.6, “Master Control Register
Freescale Semiconductor