MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1315

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

It is also acceptable to configure the burst length as the divisor of block size so that each time the burst
length is the same.
20.5.2.3
It is possible that the internal DMA engine fails during the data transfer. When an error occurs, the DMA
engine stops the transfer and goes to the idle state, while the internal data buffer stops working, too.
IRQSTAT[DMAE] is set to inform the driver.
Once the IRQSTAT[DMAE] interrupt is received, software should send CMD12 to abort the current
transfer and read DSADDR[DS_ADDR] to obtain the start address of the corrupted block. After the DMA
error is fixed, the software should apply a data reset and restart the transfer from this address to recover
the corrupted block.
20.5.3
The SD protocol unit deals with all SD protocol affairs and performs the following:
It consists of four submodules: SD transceiver, SD clock and monitor, command agent and data agent.
20.5.3.1
In the SD protocol unit, the transceiver is the main control module. It consists of a FSM and the control
module, from which the control signals for all other three modules are generated.
20.5.3.2
This module monitors the signal level on all eight data lines and the command lines, directly route the level
values into the register bank for the driver to debug with.
The transceiver reports the card insertion state according to the SDHC_CD state, or signal level on
SDHC_DAT[3] line when PROCTL[D3CD] is set.
The module detects the SDHC_WP (write protect) line. With the information of SDHC_WP state, the
register bank ignores the command accompanied by write operation, when the SD_WP switch is on.
If the internal data buffer is in danger and the SD clock must be gated off to avoid buffer over/underrun,
this module asserts the gate of output SD clock to shut the clock off. When the buffer danger is eliminated
Freescale Semiconductor
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Acts as the bridge between internal buffer and the SD bus
Sends the command data and its argument serially
Stores the serial response bit stream into corresponding registers
Detects bus state on SDHC_DAT[0] line
Asserts read wait signal
Gates off SD clock when the buffer announces danger status
Detects write-protect state
And other functions
SD Protocol Unit
CCB Master Interface
SD Transceiver
SD Clock and Monitor
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Enhanced Secure Digital Host Controller
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