MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 86

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table
Number
9-30
9-31
9-32
9-33
9-34
9-35
9-36
9-37
9-38
9-39
9-40
9-41
9-42
9-43
9-44
9-45
9-46
9-47
9-48
9-49
9-50
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-14
10-13
10-15
10-16
10-17
10-18
10-19
10-20
lxxxvi
MSGRn Field Descriptions................................................................................................... 9-35
MER Field Descriptions........................................................................................................ 9-36
MSR Field Descriptions........................................................................................................ 9-36
MSIRn Field Descriptions .................................................................................................... 9-37
MSISR Field Descriptions .................................................................................................... 9-37
MSIIR Field Descriptions ..................................................................................................... 9-38
MSIVPRn Field Descriptions ............................................................................................... 9-39
MSIDRn Field Descriptions.................................................................................................. 9-39
EIVPRn Field Descriptions................................................................................................... 9-41
EIDRn Field Descriptions..................................................................................................... 9-42
IIVPRn Field Descriptions.................................................................................................... 9-44
IIDRn Field Descriptions ...................................................................................................... 9-45
MIVPRn Field Descriptions.................................................................................................. 9-45
MIDRn Field Descriptions.................................................................................................... 9-46
Per-CPU Registers—Private Access Address Offsets .......................................................... 9-47
IPIDRn Field Descriptions.................................................................................................... 9-49
CTPRn Field Descriptions .................................................................................................... 9-49
WHOAMIn Field Descriptions ............................................................................................. 9-50
IACKn Field Descriptions .................................................................................................... 9-51
EOIn Field Descriptions........................................................................................................ 9-51
PCI Express INTx/IRQn Sharing.......................................................................................... 9-56
Example Descriptor............................................................................................................... 10-5
SEC Address Map............................................................................................................... 10-12
SEC Address Map............................................................................................................... 10-13
Header Dword Bit Definitions ............................................................................................ 10-21
Header Dword Writeback Bit Definitions........................................................................... 10-22
EU_SEL0 and EU_SEL1 Values ........................................................................................ 10-23
Descriptor Types ................................................................................................................. 10-23
Pointer Dword Field Definitions......................................................................................... 10-25
Link Table Field Definitions ............................................................................................... 10-27
Descriptor Format Summary............................................................................................... 10-30
Channel Configuration Register Fields............................................................................... 10-38
Writeback Options............................................................................................................... 10-40
Channel Status Register Field Descriptions........................................................................ 10-41
Done Interrupt Options ....................................................................................................... 10-41
Channel Status Register Error Field Definitions................................................................. 10-43
Current Descriptor Pointer Register Fields ......................................................................... 10-44
Fetch FIFO Enqueue Register Field Descriptions .............................................................. 10-44
Channel Assignment Value ................................................................................................. 10-50
Field Names in Interrupt Enable, Interrupt Status, and Interrupt Clear Registers .............. 10-51
IP Block Revision Register Fields ...................................................................................... 10-55
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Tables
Title
Freescale Semiconductor
Number
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