MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1519

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

machine check (if HID1[RFXE] = 1). If RFXE = 0, the assertion of core_fault_in does not directly cause
a machine check interrupt, but must be handled by the block that generated the error. For more information
about RFXE, see
register model chapter of the PowerPC e500 Core Family Reference Manual.
Table 23-19
23.4.1.17 Reset Request Status and Control Register (RSTRSCR)
Shown in
settable reset request bit
Freescale Semiconductor
Offset 0x094
Reset
Offset 0x090
Reset
0–28
Bits
29
30
31
W
W
R
R
0
0
SRESET Soft reset machine check
MCP_IN MCP signal asserted
Name
WRS
Figure
—
describes the bit settings of MCPSUMR.
23-17, RSTRSCR contains the status for boot sequencer, watchdog timer, and a software
Reserved
Watchdog timer machine check
0 Machine check exception was not caused by watchdog timer.
1 Machine check was caused by a soft reset condition from the e500 watchdog timer as configured in the
0 Machine check exception was not caused by SRESET assertion.
1 Machine check exception was caused by the assertion of the SRESET input signal.
0 Machine check exception was not caused by MCP assertion.
1 Machine check exception was caused by the assertion of the MCP input signal.
Section 5.3, “Summary of Core Integratation
Figure 23-17. Reset Request Status and Control Register (RSTRSCR)
core’s TSR. Specifically, TSR[WRS] = 01 and a watchdog reset condition occurred.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 23-16. Machine Check Summary Register (MCPSUMR)
8
NFLSH_RR BS_RR WDT0_RR SW_RR
9
Table 23-19. MCPSUMR Field Descriptions
10
—
11
All zeros
All zeros
Description
12
13
Details,” and the section on HID1 in the
28
WRS SRESET MCP_IN
w1c
29
Access: Read Only
w1c
30
Global Utilities
Access: w1c
w1c
23-27
31
31