MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 44

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
21.5.3.1
21.5.3.2
21.5.3.3
21.5.4
21.5.4.1
21.5.4.2
21.5.4.3
21.5.4.4
21.5.4.5
21.5.5
21.5.5.1
21.5.5.2
21.5.5.3
21.5.5.4
21.5.6
21.5.6.1
21.5.6.2
21.5.6.3
21.5.7
21.5.7.1
21.5.7.2
21.6
21.6.1
21.6.2
21.6.3
21.6.4
21.6.4.1
21.6.5
21.6.6
21.6.7
21.6.8
21.6.8.1
21.6.8.2
21.6.8.2.1
21.6.9
21.6.9.1
21.6.9.2
21.6.9.3
21.6.9.4
21.6.9.5
21.6.10
xliv
Host Operations ........................................................................................................... 21-61
Split Transaction Isochronous Transfer Descriptor (siTD)...................................... 21-47
Queue Element Transfer Descriptor (qTD) ............................................................. 21-51
Queue Head.............................................................................................................. 21-56
Periodic Frame Span Traversal Node (FSTN)......................................................... 21-60
Host Controller Initialization ................................................................................... 21-62
Power Port................................................................................................................ 21-63
Reporting Over-Current ........................................................................................... 21-63
Suspend/Resume...................................................................................................... 21-63
Schedule Traversal Rules......................................................................................... 21-66
Periodic Schedule Frame Boundaries vs. Bus Frame Boundaries........................... 21-67
Periodic Schedule .................................................................................................... 21-69
Managing Isochronous Transfers Using iTDs ......................................................... 21-70
Asynchronous Schedule........................................................................................... 21-74
Managing Control/Bulk/Interrupt Transfers via Queue Heads................................ 21-79
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Next Link Pointer ................................................................................................ 21-44
iTD Transaction Status and Control List ............................................................. 21-45
iTD Buffer Page Pointer List (Plus) .................................................................... 21-46
Next Link Pointer ................................................................................................ 21-48
siTD Endpoint Capabilities/Characteristics......................................................... 21-48
siTD Transfer State .............................................................................................. 21-49
siTD Buffer Pointer List (Plus)............................................................................ 21-50
siTD Back Link Pointer ....................................................................................... 21-51
Next qTD Pointer................................................................................................. 21-52
Alternate Next qTD Pointer................................................................................. 21-52
qTD Token ........................................................................................................... 21-53
qTD Buffer Page Pointer List .............................................................................. 21-56
Queue Head Horizontal Link Pointer .................................................................. 21-57
Endpoint Capabilities/Characteristics.................................................................. 21-57
Transfer Overlay .................................................................................................. 21-59
FTSN Normal Path Pointer.................................................................................. 21-61
FSTN Back Path Link Pointer ............................................................................. 21-61
Port Suspend/Resume .......................................................................................... 21-64
Host Controller Operational Model for iTDs ...................................................... 21-70
Software Operational Model for iTDs ................................................................. 21-72
Adding Queue Heads to Asynchronous Schedule ............................................... 21-75
Removing Queue Heads from Asynchronous Schedule...................................... 21-76
Empty Asynchronous Schedule Detection .......................................................... 21-78
Asynchronous Schedule Traversal: Start Event................................................... 21-79
Reclamation Status Bit (USBSTS Register)........................................................ 21-79
Periodic Scheduling Threshold........................................................................ 21-73
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Freescale Semiconductor
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