MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1197

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 17-128
Note that in all of these examples, the original addresses of the individual bytes within the scalars (as
created by the source) have been preserved.
17.4.1.2.1
All internal memory-mapped registers in the CCSR space use big endian byte ordering. However, the PCI
Express specification defines PCI Express configuration registers as little endian. All accesses to the PCI
Express configuration port, PEX_CONFIG_DATA, including the those targeting the internal PCI Express
configuration registers, use the address invariance policy as shown in
must access PEX_CONFIG_DATA with little-endian formatted data—either using the lwbrx/stwbrx
instructions or by manipulating the data before writing to and after reading from PEX_CONFIG_DATA.
17.4.1.3
The PCI Express link supports lane reversal.
Freescale Semiconductor
x8 link without lane reversal
x4 link without lane reversal
x2 link without lane reversal
x1 link without lane reversal
x8 link with lane reversal
PCI Express Configuration Space
Link Configuration
Address lsbs
Significance
Byte lane
Data
Lane Reversal
shows an inbound transfer of a 2-byte scalar, 0x5837, using address invariance.
Byte Order for Configuration Transactions
PEX_CONFIG_DATA
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 17-128. Address Invariant Byte Ordering—2 bytes Inbound
Table 17-120. Lane Assignment With and Without Lane Reversal
011
Figure 17-129. PEX_CONFIG_DATA Byte Ordering
—
3
Lane 0
Little endian
source bus
010
0
0
0
0
7
—
2
MSB LSB
001
58
1
Byte0
Byte3
Lane 1
MSB
—
000
1
1
1
6
37
0
Table 17-120
Lane 2
—
—
2
2
5
Byte1
Byte2
Lane 3
describes the supported configurations.
—
—
3
3
4
MSB LSB
000
37
0
destination bus
Big endian
001
58
Lane 4
1
—
—
—
4
3
Byte2
Byte1
Figure
010
—
2
011
—
Lane 5
3
17-129. Therefore, software
—
—
—
5
2
PCI Express Interface Controller
Byte3
Byte0
Lane 6
LSB
—
—
—
6
1
Lane 7
—
—
—
7
0
17-101