MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 675

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 13-22
Freescale Semiconductor
11–13
16–23
Bits
1–7
8–9
10
14
15
0
BCTLC
LPBSE
Name
EPAR
LDIS
AHD
BMT
—
—
describes LBCR fields.
Local bus disable
0 Local bus is enabled.
1 Local bus is disabled. No internal transactions will be acknowledged.
Reserved
Defines the use of LBCTL
00 LBCTL is used as W/R control for GPCM or UPM accesses (buffer control).
01 LBCTL is used as LOE for GPCM accesses only.
10 LBCTL is used as LWE for GPCM accesses only.
11 Reserved.
Address hold disable. Removes part of the hold time for LAD with respect to LALE in order to lengthen the
LALE pulse
0 During address phases on the local bus, the LALE signal negates one platform clock period prior to the
1 During address phases on the local bus, the LALE signal negates 0.5 platform clock period prior to the
Reserved.
Enables parity byte select on LGTA/LFRB/LGPL4/LUPWAIT/LPBSE signal.
0 Parity byte select is disabled. LGTA/LGPL4/LPBSE signal is available for memory control as LGPL4
1 Parity byte select is enabled. LPBSE signal is dedicated as the parity byte select output, and
Determines odd or even parity. Writing GPCM or UPM controlled memory with EPAR = 1 and reading the
memory with EPAR = 0 generates parity errors for testing.
0 Odd parity; normal, odd-parity ECC
1 Even parity; inverted, even-parity ECC
Bus monitor timing. Defines the bus monitor time-out period. Clearing BMT (reset value) selects the
maximum count of bus clock cycles. For non-zero values of BMT, the number of LCLK clock cycles to count
down before a time-out error is generated is given by:
bus cycles = BMT × PS, where PS is set according to LBCR[BMTPS].
The value of BMT × PS must not be less than 40 bus cycles for reliable operation.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
address being invalidated. For instance, at 33.3 MHz, this provides 3 ns of additional address hold time
at the external address latch.
address being invalidated. This halves the address hold time, but extends the latch enable duration. This
may be necessary for very high frequency designs.
(output) or LGTA/LFRB/LUPWAIT (input).
LGTA/LFRB/LUPWAIT is disabled.
Table 13-22. LBCR Field Descriptions
Description
Enhanced Local Bus Controller
13-33