MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 914

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
The definition of the 8-byte received preamble sequence is shown in
The fields of the received preamble sequence are described in
be shorter than the 7-octet sequence defined by IEEE Std. 802.3, initial bytes of the received preamble
sequence hold undefined values. The standard start of frame delimiter (0xD5) is always omitted. Note that
preamble extraction is not possible in RMII mode.
14.6.3.6
Using promiscuous mode, the eTSEC can automatically gather network statistics required for remote
network interface monitoring. The RMON MIB group 1, RMON MIB group 2, RMON MIB group 3,
RMON MIB group 9, RMON MIB2, and the IEEE 802.3 Ethernet MIB are supported. For RMON
statistics and their corresponding counters, see the memory map.
14.6.3.7
The Ethernet controller performs frame recognition using destination address (DA) recognition. A frame
can be rejected or accepted based on the outcome.
14-166
Bytes
Byte Offsets
0–1
2–3
4–5
6–7
0–1
2–3
4–5
6–7
8–15
8–15
8–15
8–15
Bits
0–7
0–7
0–7
0–7
RMON Support
Frame Recognition
PreOct0 Octet #0 of received preamble. This is the first octet of preamble received.
PreOct1 Octet #1 of received preamble. This is the second octet of preamble received.
PreOct2 Octet #2 of received preamble. This is the third octet of preamble received.
PreOct3 Octet #3 of received preamble. This is the fourth octet of preamble received.
PreOct4 Octet #4 of received preamble. This is the fifth octet of preamble received.
PreOct5 Octet #5 of received preamble. This is the sixth octet of preamble received.
PreOct6 Octet #6 of received preamble. This is the seventh octet of preamble received. The last octet (the
0
Name
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
1
Figure 14-142. Definition of Received Preamble Sequence
start of frame delimiter) is discarded.
Reserved
Table 14-151. Received Preamble Field Descriptions
2
PreOct0
PreOct2
PreOct4
PreOct6
3
4
5
6
7
Description
Table
8
9
14-151. Should the received preamble
Figure
10
14-142.
11
PreOct1
PreOct3
PreOct5
12
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14
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