MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 502

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
Context and Operation for XCBC-MAC Cipher Mode
XCBC-MAC cipher mode is an authentication-only mode of AES. Normal CBC-MAC runs AES in CBC
cipher mode and assigns the final ciphertext result as the MAC. XCBC-MAC supports only 16-byte keys
and extends the normal CBC-MAC as follows:
1. 3 keys are precomputed
2. Compute C
3. If |P
In XCBC-MAC cipher mode, AUX0=1 means that the final data block is not XORed with K2 or K3, so
that message processing can be interrupted and later continued after a context switch. AUX1=1 disables
computation of keys K1, K2, and K3, and instead expects these keys to be placed in key registers 5–6 (K1),
context registers 7–8 (K2) and 9–10 (K3). If AUX1=0, computed keys are placed into context registers
5–10. AUX2=1 enables XCBC-MAC with ICV. In XCBC-MAC with ICV, the received MAC is supplied
in context registers 3–4 and compared to the computed MAC in context registers 1–2.
Operation of the AESU in XCBC-MAC cipher mode requires the following steps (note these steps are
performed automatically in channel-driven access):
10-72
1.Notation: {01}
1. Reset
2. Program the mode register as follows:
then: MAC = AES-CBC (
else: MAC = AES-CBC (
a.
b.
c.
a.
b. Set AUX0 = 1 if processing of the message is going to be interrupted and later continued after
n
| = block size (128 bits)
K1 = AES-Encrypt (K, {0x01}
K2 = AES-Encrypt (K, {0x02}
K3 = AES-Encrypt (K, {0x03}
Set the cipher mode to XCBC-MAC (encode/decode bit is ignored)
a context switch. Set AUX0 = 0 if this is the last (or only) part of the message so that the final
MAC can be generated.
16
n-1
means the byte 0x01 repeated 16 times
Notes:
Context register 12 is unused for these modes
* Used only in ICV mode—must be written at start of new message for ICV checking
C
T
Context Register #
= AES-CBC (P
Length of total data (in bits)
Table 10-30. AESU Context Registers for Integrity Modes (continued)
Length of data processed with current descriptor (in bits)
(byte address)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
11 (0x34150)
P
P
n
n
1
10
, 0, K1) ... AES-CBC (P
K2
i
XCBC-MAC
, C
K3
n-1
16
16
16
Cipher Mode providing only Data Integrity
, C
).
).
).
, K1)
1
n-1
, K1)
GCM-GHASH
len(AAD)
n-1
, C
n-2
C
, K1)
CMAC (OMAC1)
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