MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 519

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.2.1
As shown in
AFEU. The mode register is cleared when the AFEU is reset or re-initialized. Setting a reserved mode bit
generates a data error. If the mode register is modified during processing, a context error is generated.
Table 10-37
10.7.2.2
As displayed in
in performing S-box permutation. Any key data beyond the number of bytes in the key size register is
ignored. This register is cleared when the AFEU is reset or re-initialized. If the key size specified is less
than 1 or greater than 16, a key size error is generated. If the key size register is modified during processing,
a context error is generated. Note: Although the AFEU supports key lengths as short as 1 byte, a 1 byte key
offers little security. Most applications of ARC4 specify keys of 5-16 bytes.
Freescale Semiconductor
Offset 0x3_8000
Reset
W
R
The following bits are described for information only. They are not under direct user control.
The following bits are controlled through the MODE0 field of the descriptor header.
56–60
0–55
Bits
0
61
62
63
describes AFEU Mode Register fields.
Figure
AFEU Mode Register
AFEU Key Size Register
Figure
Name
CS
DC
—
—
PP
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
10-32, the AFEU mode register contains three bits which are used to program the
20-60, this value indicates the number of bytes of key memory that should be used
Table 10-37. AFEU Mode Register Field Descriptions
Reserved
Reserved
Context Source. If set, this causes the context to be moved from the input FIFO into the
S-box prior to starting encryption/decryption. Otherwise, context should be directly
written to the context registers or context should be generated automatically through
key permutation. Context source is only checked if the prevent permute bit is set.
0 Context not from FIFO (written directly to context register addresses)
1 Context from input FIFO
Dump Context. If set, this causes the context to be moved from the S-box to the output
FIFO following assertion AFEU’s done interrupt.
0 Do not dump context
1 After cipher, dump context
Prevent Permute. Normally, AFEU receives a key and uses that information to
randomize the S-box. If reusing a context from a previous descriptor, this bit should be
set to prevent AFEU from re-performing this permutation step.
0 Perform S-box permutation
1 Do not permute
Figure 10-32. AFEU Mode Register
—
All zeros
Description
Security Engine (SEC) 3.0
Access: Read/Write
60 61
CS DC PP
62
10-89
63