MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1705

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Index
Universal asynchronous receiver/transmitter, see DUART
Universal serial bus, see USB interface
UPWAIT (LBC UPM wait) signal, 13-7, 13-75
USB interface
Freescale Semiconductor
asynchronous schedule, 21-41, 21-74
features, 21-2
frame list
functional descriptions
host data structures, 21-41
host operations, 21-61
isochronous (high-speed) transfer descriptor (iTD), 21-41,
memory map/register definitions, 21-4–21-5, ??–A-19
modes of operation, 21-2
adding queue heads, 21-75
empty detection, 21-78
list queue head pointer, 21-43
organization, 21-43
reclamation status bit, 21-79
removing queue heads, 21-76
traversal (start event), 21-79
link pointer format, 21-43
DMA engine, 21-40
FIFO RAM controller, 21-41
PHY interface, 21-41
system interface, 21-40
behavior during wake-up events, 21-65
host controller initialization, 21-62
periodic schedule, 21-69
periodic schedule frame boundaries vs. bus frame
port power control (PPC), 21-63
port suspend/resume, 21-64
reporting over-current, 21-63
schedule traversal rules, 21-66
split transactions, 21-84
suspend/resume, 21-63
buffer page pointer list (plus), 21-46
host controller operational model, 21-70
managing transfers, 21-70
next link pointer, 21-44
periodic scheduling threshold, 21-73
software operational model, 21-72
transaction status and control list, 21-45
execution state machine for isochronous, 21-104
isochronous, 21-98
periodic interrupt—Do-Complete-Split, 21-94
periodic interrupt—Do-Start-Split, 21-93
scheduling mechanisms for isochronous, 21-99
see also USB interface, split transactions
tests for execution, 21-94
tracking progress for isochronous transfers, 21-102
21-44
boundaries, 21-67
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
V
Voltage selection
overview, 21-2
periodic frame list, 21-41, 21-42
periodic frame span traversal node (FSTN), 21-60
periodic schedule, 21-41, 21-42
queue element transfer descriptor (qTD), 21-41, 21-51
queue heads, 21-41, 21-56
registers
signals, 21-2–21-4
split transaction isochronous transfer descriptor (siTD),
split transactions, 21-84
LBC signals, 23-31
back path link pointer, 21-61
normal path pointer, 21-61
organization, 21-42
rebalancing, 21-98
alternate next pointer, 21-52
buffer page pointer list, 21-56
next pointer, 21-52
token, 21-53
endpoint capabilities/characteristics, 21-57
horizontal link pointer, 21-57
managing control/bulk/interrupt transfers, 21-79
managing the QH[FrameTag] field, 21-97
transfer overlay, 21-59
by acronym, see Register Index
capability registers, 21-6–21-10
operational registers, 21-10
ULPI interface, 21-2
back link pointer, 21-51
buffer pointer list (plus), 21-50
endpoint capabilities/characteristics, 21-48
next link pointer, 21-48
transfer state, 21-49
asynchronous transfers, 21-84
interrupt, 21-86
buffer pointer list use for data streaming with qTDs,
ping control, 21-83
to the periodic schedule, 21-82
transfer complete interrupts, 21-82
21-41, 21-47
Do-Complete-Split state, 21-85
Do-Start-Split state, 21-85
execution state machine, 21-92
host controller operational model for FSTNs, 21-89
scheduling mechanisms, 21-86
software operational model for FSTNs, 21-91
tracking progress for interrupt transfers, 21-92
21-80
Index-19
V–V