MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 258

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

L2 Look-Aside Cache/SRAM
Table 6-28
L2. The transaction types and attributes listed follow MPX bus nomenclature, with the addition of write
allocate (burst write with L2 cache allocation).
pushes triggered by snoops, listed in
6-38
dcbf
dcbst
icbi
Source of Transaction
Read, snoop local processor
Read, unlock L2 cache line
Write
Write <
Write, allocate L2 cache line 32-byte
Write, allocate L2 cache line < 32-byte I/T
Write, allocate and lock L2 cache line
32-byte
Write, allocate and lock L2 cache line
< 32-byte
ATOMIC increment, decrement, set,
and clear
32-byte
lists L2 cache state transitions for all system-initiated (non-core) transactions that change the
32-byte
Transaction Type
Table 6-27. State Transitions Due to Core-Initiated Transactions (continued)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 6-28. State Transitions Due to System-Initiated Transactions
Initial States
dL1
iL1
I,E
I,V
L1
E/EL/T
E/EL/T
Table
I/T
E
EL
I/T
E/EL
I/E/EL/T
I
E/EL
T
I/E/EL/T
I/E
EL/T
I/T
E/EL
E/EL
I/E
EL/T
E/EL
I/E/EL/T
I/T
E/EL
I/E
EL/T
L2
I/
I/
Initial L2
State
6-27.
Hit
No
No
L2
Table 6-28
Same
E
EL
I
E
I
E
Same
EL
EL
I
T
Same
Same
EL
E
EL
Same
Same
EL
Same
EL
I
T
Final States
L1
Final L2
I
I
State
L2
I
I
accounts for changes caused by L1 snoop
Miss in cache external write (CEW) windows
Hit in CEW window
Hit in CEW window (CEW lock attribute set)
Miss in CEW windows
Hit in CEW window (no data is written)
(regardless of CEW lock attribute)
Hit in CEW window
Hit in CEW window (CEW lock attribute set)
Allocate regardless of CEW window
No data is written
Allocate and lock regardless of CEW window
No data is written
Invalidate line
Invalidate data, keep lock
Comments
Comments
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