MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 188

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
Note that the value latched on this signal during POR is accessible through the memory-mapped
PORBMSR (POR boot mode status register) described in
Register (PORBMSR).”
Note also that the value latched on this signal during POR affects the PCI agent lock mode (See
Section 16.3.2.19, “PCI Bus Function Register
Register (See
4.4.3.11
The boot sequencer configuration options, shown in
configuration data from the serial ROM located on the I
MPC8536E. These options also specify normal or extended I
“Boot Sequencer Mode,”
Note that the values latched on these signals during POR are accessible through the memory-mapped
PORBMSR (POR boot mode status register) described in
Register (PORBMSR).”
4-18
Functional
Default (1)
LGPL3/LFWP,
Default (11)
Functional
Signal
LA27
Signal
LGPL5
Boot Sequencer Configuration
Section 17.3.10.18, “Configuration Ready
Reset Configuration
When the boot sequencer is enabled, the processor core will be held in reset
and thus prevented from fetching boot code until the boot sequencer has
completed its task, regardless of the state of the CPU boot configuration
signal described in
Reset Configuration
cfg_cpu_boot
cfg_boot_seq[0:1]
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Name
Name
for more information on the boot sequencer.
Table 4-19. Boot Sequencer Configuration
Section 4.4.3.10, “CPU Boot
Table 4-18. CPU Boot Configuration
(Binary)
Value
(Binary)
Value
0
1
00
01
10
11
CPU boot holdoff mode. The e500 core is prevented from booting until
configured by an external master.
The e500 core is allowed to boot without waiting for configuration by an
external master (default).
Reserved
Normal I
loads configuration information from a ROM on the I
ROM must be present.
Extended I
loads configuration information from a ROM on the I
ROM must be present.
Boot sequencer is disabled. No I
(PBFR).”) and the PCI Express Configuration Ready
NOTE
2
Table
C addressing mode is used. Boot sequencer is enabled and
2
C addressing mode is used. Boot sequencer is enabled and
2
Register—0x4B0.”).
C1 port before the host tries to configure the
Section 23.4.1.2, “POR Boot Mode Status
Section 23.4.1.2, “POR Boot Mode Status
4-19, allow the boot sequencer to load
2
C addressing modes. See
Configuration.”
Meaning
Meaning
2
C ROM is accessed (default).
Freescale Semiconductor
2
Section 11.4.5,
2
C1 interface. A valid
C interface. A valid