MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1042

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
Each window contains a base address that points to the beginning of the window in the local address map,
a translation address that specifies the high-order bits of the transaction in the external PCI address space,
and a set of attributes including window size and external transaction type.
Each window must be aligned based on the granularity specified by the window size. If two outbound
ATMU windows overlap in the local address space, the mapping of the lower numbered window has
precedence over the higher numbered window.
Window 0 is the default window and is the only window enabled upon reset. The default outbound register
set is used when a transaction misses in all of the other outbound windows.
16.3.1.2.1
The PCI outbound translation address registers (POTARn) select the starting addresses in the PCI address
space for hits in the PCI outbound windows. The translated address is created by concatenating the
transaction offset to this translation address. The format of the POTARn is shown in
Table 16-7
16.3.1.2.2
The PCI outbound translation extended address registers (POTEARn) contain the most significant bits of
a 64-bit translation address. The format of POTEARn is shown in
Table 16-8
16-16
Offset 0xC00, 0xC20, 0xC40, 0xC60, 0xC80
Offset 0xC04, 0xC24, 0xC44, 0xC64, 0xC84
Reset
Reset
12–31
0–11
W
Bits Name
W
R
R
0
0
TEA Translation extended address. Represents bits [43:32] of a 64-bit PCI address (bit 0 is lsb).
describes the fields of the POTARn registers.
describes the fields of the POTEARn.
TA
Figure 16-7. PCI Outbound Translation Extended Address Registers (POTEAR n )
PCI Outbound Translation Address Registers (POTAR n )
PCI Outbound Translation Extended Address Registers (POTEAR n )
Translation address. Represents bits [31:12] of the PCI address. The specified address must be aligned
to the window size, as defined by POWAR n [OWS].
Figure 16-6. PCI Outbound Translation Address Registers (POTAR n )
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
TEA
—
Table 16-7. POTAR n Field Descriptions
11 12
11 12
All zeros
All zeros
Description
Figure
TEA
TA
16-7.
Freescale Semiconductor
Figure
Access: Read/Write
Access: Read/Write
16-6.
31
31