MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 926

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
In the case of RxBD rings, FCBs are inserted by the eTSEC whenever RCTRL[PRSDEP] is set to a
non-zero value. Only one FCB is inserted per frame, in the buffer pointed to by the RxBD with bit F set.
TOE acceleration for receive is enabled for all frames in this case.
14.6.4.2
TOE functions for transmit are defined by the contents of the Tx FCB.
definition for the Tx FCB.
The user instructs the Tx packet to be timestamped via setting bit 15 in the TxFCB to mark a PTP packet.
TxFCB[VLCTL] can be translated as the Tx PTP packet identification number. BD[TOE] has to be set to
enable transmit PTP packet time stamping. TxFCB[PTP] bit takes precedence over TxFCB[VLN] bit. It
disables per packet VLAN tag insertion. On a PTP packet, VLAN tag can be inserted from the DFVLAN
register. A proposed TxFCB update for the PTP packet is shown in
The contents of the Tx FCB are defined in
14-178
Bytes
0–1
Offset + 0
Offset + 2
Offset + 4
Offset + 6
Bits
0
1
2
3
4
Transmit Path Off-Load and Tx PTP Packet Parsing
VLN
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Name
UDP
VLN
TUP
IP6
IP
IP
1
IP6
Table 14-158. Tx Frame Control Block Description
2
VLAN control word valid. This bit is ignored when the PTP bit is set. VLAN tag is read from
the DFVLAN register if PTP=1.
0 Ignore VLCTL field.
1 If VLAN tag insertion is enabled for eTSEC, use the VLCTL field as the VLAN control
Layer 3 header is an IP header.
0 Ignore layer 3 and higher headers.
1 Assume that the layer 3 header is an IPv4 or IPv6 header, and take L3OS field as valid.
IP header is IP version 6. Valid only if IP = 1.
0 IP header version is 4.
1 IP header version is 6.
Layer 4 header is a TCP or UDP header.
0 Do not process any layer 4 header.
1 Assume that the layer 4 header is either TCP or UDP (see UDP bit), and offload
UDP protocol at layer 4.
0 Layer 4 protocol is either TCP (if TUP = 1) or undefined.
1 Layer 4 protocol is UDP if TUP = 1.
Figure 14-146. Transmit Frame Control Block
word.
checksumming on the basis that the IP header has no extension headers.
TUP UDP CIP CTU NPH
3
L4OS
4
Table
5
14-158.
6
7
VLCTL
PHCS
8
Description
9
Figure
10
Figure 14-146
14-153.
11
L3OS
12
Freescale Semiconductor
describes the
13
14
PTP
15