MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1364

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.3.2.16 Endpoint Setup Status Register (ENDPTSETUPSTAT)—Non-EHCI
This register is not defined in the EHCI specification. This register contains the endpoint setup status. It is
only used in device mode.
21-30
31–5
Offset 0x1AC
Reset
Bits
1–0
4
3
2
W
R
SLOM Setup lockout mode. In device mode, this bit controls behavior of the setup lock mechanism. See
Name
31
SDIS
CM
—
—
Reserved, should be cleared.
Stream disable
Host mode:
1 Active.
0 Inactive.
Device mode:
Section 21.8.3.5, “Control Endpoint Operation Model.”
1 Setup lockouts off. DCD requires use of setup data buffer tripwire in USBCMD (SUTW).
0 Setup lockouts on
Reserved, should be cleared.
Controller mode
This register can only be written once after reset. If it is necessary to switch modes, software must reset the
controller by writing to USBCMD[RST] before reprogramming this register.
00 Idle (default for combination host/device).
01 Reserved
10 Device controller (default for device only controller).
11 Host controller (default for host only controller).
Defaults to the idle state and needs to be initialized to the desired operating mode after reset.
• Setting this bit ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems
• Note that time duration to pre-fill the FIFO becomes significant when stream disable is active. See
• Also note that in systems with high system bus utilization, setting this bit will ensure no overruns or underruns
• Setting this bit disables double priming on both RX and TX for low bandwidth systems. This mode ensures
• Note that in high-speed mode, all packets received will be responded to with a NYET handshake when stream
where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the
effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB.
TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature.
during operation, at the expense of link utilization. For those who desire optimal link performance, SDIS can
be left clear, and the rules used under the description of the TXFILLTUNING register to limit
underruns/overruns.
that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering
scheme is disabled to prevent overruns/underruns in bandwidth limited systems.
disable is active.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 21-22. Endpoint Setup Status (ENDPTSETUPSTAT)
Table 21-23. USBMODE Register Field Descriptions
—
All zeros
Description
6
5
Freescale Semiconductor
ENDPTSETUPSTAT
Access: Read/Write
0