MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1550

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
23.5.1.14.2 GPIO
The GPIO wake up event occurs according to configuration by the e500 software to generate an interrupt.
The GPIO interrupt is connected to the OpenPIC to generate a wake up interrupt.
23.5.1.14.3 Timer
The timer wake up event occurs according to configuration by the e500 software to generate an interrupt
when the timer expires.
The timer interrupt is connected to the OpenPIC to generate a wake up interrupt.
The timer facilities are not available when the device is in sleep or deep sleep modes since either the clock
to the e500 core will be gated off or the power to the e500 core will be removed.
23.5.1.14.4 eTSEC Wake-on LAN—Magic Packet
The eTSEC supports two types of wake-up events:
Note that the eTSEC cannot supports both types of wake-up event simultaneously.
When wake-up on Magic Packet is desired, prior to entering sleep or deep sleep, the user should set the
Magic packet enable bit in the Ethernet controller (MACCFG2[MPEN]) and clear the eTSEC clock
disable bit in the PMCDR register (PMCDR[etsecX] = 0, where X = 1 or 3, for the eTSEC(s) that is being
used for the magic packet). The Ethernet MAC blocks receives all traffic to the system and hunts for magic
packet (ignoring all received frames except the magic packet). When a Magic packet is detected then the
Magic packet enable bit is automatically cleared by the MAC hardware and set the wake up interrupt to
the power management controller.
The user should configure the interrupt controller to enable the eTSEC error interrupt (which may be
generated either when a Magic packet is received, or in various other error situations). It is the user’s
responsibility to determine for their system which error interrupts should be masked, and which are critical
errors that should be used as wakeup events.
Note that if the user configured the Ethernet MAC to wake-up on Magic packet but the MPC8536E exits
low power mode by other wake-up event source, it is the user responsibility to clear the Magic packet
enable bit, otherwise the Ethernet received traffic is blocked.
While in Magic Packet mode, the eTSEC will not initiate any traffic to DDR. The user should set
DDR_SDRAM_CFG[SREN] = 1 and optionally can also program DDR_SR_CNTR[SR_IT] to a non-zero
value.
When a Magic Packet is received, an interrupt is generated and the eTSEC hardware automatically clears
MACCFG2[MPEN]. However, transactions after the magic packet continue to be dropped until the core
wakes and the entire device comes out of its low-power mode. Therefore there is no chance of buffer
overflow.
23-58
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Magic Packet
ARP (user-defined) Packet
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor