MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1453

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.7.1.2
The seven DWords in the overlay area represent a transaction working space for the device controller. The
general operational model is that the device controller can detect whether the overlay area contains a
description of an active transfer. If it does not contain an active transfer, then it will not read the associated
endpoint.
After an endpoint is readied, the dTD will be copied into this queue head overlay area by the device
controller. Until a transfer is expired, software must not write the queue head overlay area or the associated
transfer descriptor. When the transfer is complete, the device controller will write the results back to the
original transfer descriptor and advance the queue.
See dTD for a description of the overlay fields.
21.7.1.3
The current dTD pointer is used by the device controller to locate the transfer in progress. This word is for
the USB controller (hardware) use only and should not be modified by DCD software.
21.7.1.4
The set-up buffer is dedicated storage for the 8-byte data that follows a set-up PID.
Freescale Semiconductor
26–16
14–0
31–5
Bits
Bits
4–0
15
Current dtd. This field is a pointer to the dTD that is represented in the transfer overlay area. This field will be modified
by the Device Controller to next dTD pointer during endpoint priming or queue advance.
Reserved, should be cleared. Bit reserved for future use and should be cleared.
Maximum
Length
Packet
Name
ios
Transfer Overlay
Current dTD Pointer
Set-up Buffer
Each endpoint has a TX and an RX dQH associated with it, and only the RX
queue head is used for receiving setup data packets.
Maximum packet length. This directly corresponds to the maximum packet size of the associated endpoint
(wMaxPacketSize). The maximum value this field may contain is 0x400 (1024).
Interrupt on setup (IOS). This bit is used on control type endpoints to indicate if USBINT is set in response
to a setup being received.
Reserved, should be cleared. Bits reserved for future use and should be cleared.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 21-74. Endpoint Capabilities/Characteristics (continued)
Table 21-75. Current dTD Pointer
NOTE
Description
Description
Universal Serial Bus Interfaces
21-119