MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 268

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

e500 Coherency Module
Table 7-5
7.2.1.5
The ECM error detect register (EEDR) is shown in
Table 7-6
7-6
Offset 0x0_1E00
Reset
16–23
24–31
8–15
1–30
Bits
Bits
0–7
31
W
R MULT_ERR
0
describes EIPBRR2 fields.
describes EEDR fields.
MULT_ERR Multiple error. Indicates the occurrence of multiple errors of the same type. Write 1 to clear.
w1c
Name
IP_CFG
0
IP_INT
LAE
Name
—
—
ECM Error Detect Register (EEDR)
—
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0 Multiple errors of the same type were not detected.
1 Multiple errors of the same type were detected.
Reserved
Local access error. Write 1 to clear. Two cases can generate LAEs:
0 Local access error has not occurred.
1 Local access error occurred.
• Transaction does not map to any target. In this case the ECM injects read responses (with the
• Source and target IDs indicate that an OCN port initiated a transaction that targets an OCN
Reserved
IP block integration options
Reserved
IP block configuration options
corrupt attribute set) and write data is dropped. Note that a read that attempts to access an
unmapped target causes the assertion of core_fault_in , which causes the core to generate a
machine check interrupt, unless it is disabled (by clearing HID1[RFXE]). If RFXE is zero and
this error occurs, EEER[LAEE] must be set to ensure that an interrupt is generated. For more
information, see
the PowerPC™ e500 Core Family Reference Manual .
port. This loopback behavior can result from programming errors where inbound ATMU window
targets are inconsistent with targets configured in the local access windows for a given address
range. For this type of LAE, the dispatch (to OCN target in this case) is not screened off; the
LAE error is reported, but the transaction is still sent to its OCN target.
Figure 7-6. ECM Error Detect Register (EEDR)
Table 7-5. EIPBRR2 Field Descriptions
Table 7-6. EEDR Field Descriptions
Section 5.2, “e500 Core Integration and the Core Complex Bus
Figure
All zeros
Description
Description
—
7-6.
Freescale Semiconductor
(CCB),” and
Access: w1c
30
LAE
w1c
31