MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1374

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.4
The USB DR module can be broken down into functional sub-blocks, which are described below.
21.4.1
The system interface block contains all the control and status registers that allow a processor to interface
to the USB module. These registers allow the processor to control the configuration of the module,
ascertain the capabilities of the module, and control the module’s operation. It also has registers to control
snoopability and priority of the DMA interface.
21.4.2
The module contains a local DMA engine. The DMA engine interfaces internally to the system bus. It is
responsible for moving all of the data to be transferred over the USB between the module and buffers in
system memory. Like the system interface block, the DMA engine block uses a simple synchronous bus
signaling protocol that eases connections to a number of different standard buses.
21-40
16–28
0–14
Bits
15
29
30
31
Functional Description
ULPI_INT_EN
WU_INT_EN
USB_EN
System Interface
DMA Engine
WU_INT
Name
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
Reflects the state of the wake up interrupt. The wake up interrupt signal is asserted when a
wake-up event occurs while in a low-power suspend state. If WU_INT_EN is set, this WU_INT
signal generates an interrupt to the system to indicate wake up servicing is required. WU_INT will
remain set until the USB controller is exited from the low power by clearing the PORTSC[PHCD]
bit.
0 Normal operation or Low Power mode waiting for wakeup event
1 Low power wakeup event has occurred
Reserved
Used to enable the USB interface. In safe mode, all USB interface signals are put into input mode
or driven inactive, except for SUSPEND_STP which is driven high. Also, the input signal
USB n _DIR is forced to appear asserted to the controller. This prevents any start-up problems that
otherwise could occur if the PHY and the controller take significantly different times to complete
power-on reset.
1 Normal operation.
0 Safe mode.
This bit is used to mask/unmask the system wakeup interrupt signal
0 System wakeup interrupt disabled
1 System wakeup interrupt enabled
Note: PORTSC[PHCD] bit must be set for the system wakeup interrupt generation.
Used to enable the ULPI low power wakeup interrupt from the PHY when the PHY is in low power
mode only.
0 ULPI low power wakeup interrupt disabled
1 ULPI low power wakeup interrupt enabled
Note: PORTSC[PHCD] bit must be set
Table 21-35. CONTROL Field Descriptions
Description
Freescale Semiconductor