MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1388

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21-54
11–10
Bits
9–8
PID Code
Name
Cerr
Error counter. 2-bit down counter that keeps track of the number of consecutive errors detected while
executing this qTD. If this field is programmed with a non-zero value during set-up, the host controller
decrements the count and writes it back to the qTD if the transaction fails. If the counter counts from one
to zero, the host controller marks the qTD inactive, sets the Halted bit to a one, and error status bit for the
error that caused Cerr to decrement to zero. An interrupt will be generated if USBINTR[UEE] is set. If the
host controller driver (HCD) software programs this field to zero during set-up, the host controller will not
count errors for this qTD and there will be no limit on the retries of this qTD. Note that write-backs of
intermediate execution state are to the queue head overlay area, not the qTD.
Transaction Error
Data Buffer Error
Stalled
Babble Detected
No Error
This field is an encoding of the token, which should be used for transactions associated with this transfer
descriptor. Encodings are:
00 OUT Token generates token (E1H)
01 IN Token generates token (69H)
10 SETUP Token generates token (2DH) (undefined if endpoint is an Interrupt transfer type, for example.
11 Reserved, should be cleared
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
µFrame S-mask field in the queue head is non-zero.)
Error
Table 21-53. qTD Token (DWord 2) (continued)
Yes
No. Data buffer errors are host problems. They don't count against the device's retries.
Note that software must not program Cerr to a value of zero when the EPS field is
programmed with a value indicating a full- or low-speed device. This combination could
result in undefined behavior.
No. Detection of babble or stall automatically halts the queue head. Thus, count is not
decremented
No. Detection of babble or stall automatically halts the queue head. Thus, count is not
decremented
No. If the EPS field indicates a HS device or the queue head is in the asynchronous
schedule (and PIDCode indicates an IN or OUT) and a bus transaction completes and
the host controller does not detect a transaction error, then the host controller should
reset Cerr to extend the total number of errors for this transaction. For example, Cerr
should be reset with maximum value (0b11) on each successful completion of a
transaction. The host controller must never reset this field if the value at the start of the
transaction is 0b00.
Description
Decrement Counter
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