MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 422

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller (PIC)
9.4
This section is a functional description of the PIC.
9.4.1
Figure 9-50
that this diagram describes a conceptual model of an PIC on a single processor. This logic is replicated for
each implemented processor. This conceptual diagram does not fully represent all internal circuitry of the
implementation.
This figure focusses especially on the OpenPIC-defined logic and shows how the PIC controls interrupt
requests that target the int signal. The flow in
bottom how the destination register associated with each source determines the path.
9.4.1.1
Interrupt requests routed to cint or IRQ_OUT bypass the logic that is dedicated to interrupt sources that
compete for int. That is, if xIDRn[CIn] or xIDRn[EP] = 1, corresponding xIVPR field settings have no
hardware effects; however, an interrupt handler may be able to make use of some of those fields.
cint signals are connected to the respective core’s critical interrupt input.
9.4.1.2
As shown in
within the PIC itself. As
timer and timer processor interrupts can be directed only to int.
The sources’ mask bits (xVPRn[MSK]) are tracked in the internal mask register. If a source’s MSK bit is
set, the mask register prevents the PIC from asserting int on its behalf.
Unmasked interrupt requests are qualified and latched in the interrupt pending register (IPR), an internal
interrupt summary register with a bit for each source. If an interrupt request is multi-cast, a bit is set in the
IPR for each targeted processor. Although the IPR cannot be read by software, when an IPR bit is set, the
corresponding source’s activity bit (xVPRn[A]) is automatically set.
The interrupt selector monitors the IPR and the in-service register (ISR), which tracks previously taken
interrupts that were superseded by a higher-priority interrupt before the interrupt handler finished. The
interrupt selector recognizes the highest priority unmasked interrupt request and latches it into the interrupt
9-52
Functional Description
Flow of Interrupt Control
shows the flow of interrupts directed by the PIC to the int, cint, and IRQ_OUT outputs. Note
Figure
Interrupts Routed to cint or IRQ_OUT
Interrupts Routed to int
Because interrupt sources routed to cint or IRQ_OUT must be level
sensitive, EIVPR[S] should be set. See
Vector/Priority Registers (EIVPR0–EIVPR11).”
Because these interrupts bypass the OpenPIC logic, it is especially
important that handlers do not read IACK. Doing so causes a spurious
interrupt. Likewise, they should not write EOI.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
9-50, the PIC receives interrupt requests from external and internal sources and from
Figure 9-50
shows, all of these interrupt sources can be routed to int; the global
Figure 9-50
NOTES
Section 9.3.7.1, “External Interrupt
is from the bottom to the top, and shows at the
Freescale Semiconductor