MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 29

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
14.6.5.3.1
14.6.5.3.2
14.6.6
14.6.6.1
14.6.6.2
14.6.6.2.1
14.6.6.2.2
14.6.7
14.6.7.1
14.6.7.2
14.6.7.3
14.6.7.3.1
14.6.7.4
14.6.7.4.1
14.6.7.5
14.6.7.5.1
14.6.7.5.2
14.6.7.6
14.6.8
14.6.8.1
14.6.8.2
14.6.8.3
14.7
14.7.1
14.7.1.1
14.7.1.2
14.7.1.3
14.7.1.4
14.7.1.5
14.7.1.6
14.7.1.7
14.7.1.8
15.1
15.1.1
15.1.2
15.1.3
15.1.4
Freescale Semiconductor
Initialization/Application Information ....................................................................... 14-207
Introduction.................................................................................................................... 15-1
Lossless Flow Control ........................................................................................... 14-191
Hardware Assist for IEEE Std. 1588-CompatibleTimestamping .......................... 14-194
Buffer Descriptors.................................................................................................. 14-200
Interface Mode Configuration ............................................................................... 14-207
Block Diagram........................................................................................................... 15-1
Overview.................................................................................................................... 15-2
Features...................................................................................................................... 15-2
Modes of Operation ................................................................................................... 15-2
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Back Pressure Determination through Free Buffers .......................................... 14-191
Features.............................................................................................................. 14-194
Timer Logic Overview....................................................................................... 14-195
Time-Stamp Insertion on the Received Packets ................................................ 14-195
PTP Packet Parsing ............................................................................................ 14-196
Time-Stamp Insertion on Transmit Packets....................................................... 14-197
Tx PTP Packet Parsing....................................................................................... 14-199
Data Buffer Descriptors ..................................................................................... 14-201
Transmit Data Buffer Descriptors (TxBD) ........................................................ 14-202
Receive Buffer Descriptors (RxBD).................................................................. 14-205
MII Interface Mode............................................................................................ 14-208
GMII Interface Mode......................................................................................... 14-212
TBI Interface Mode ........................................................................................... 14-216
RGMII Interface Mode ...................................................................................... 14-220
RMII Interface Mode......................................................................................... 14-224
RTBI Interface Mode......................................................................................... 14-228
8-Bit FIFO Mode ............................................................................................... 14-232
SGMII Interface Support ................................................................................... 14-234
Software Use of Hardware-Initiated Back Pressure .......................................... 14-193
Priority-Based Queuing (PBQ)...................................................................... 14-190
Modified Weighted Round-Robin Queuing (MWRR) .................................. 14-190
Initialization................................................................................................... 14-193
Operation ....................................................................................................... 14-193
Timestamp Point ............................................................................................ 14-195
General Purpose Filer Rule............................................................................ 14-197
Interrupts........................................................................................................ 14-197
Error Condition.............................................................................................. 14-199
DMA Controller
Contents
Chapter 15
Title
Number
Page
xxix