MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 620

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DUART
12.1.2
The communication channel provides a full-duplex asynchronous receiver and transmitter using an
operating frequency derived from the platform clock.
The transmitter accepts parallel data from a write to the transmitter holding register (UTHR). In FIFO
mode, the data is placed directly into an internal transmitter shift register of the transmitter FIFO. The
transmitter converts the data to a serial bit stream inserting the appropriate start, stop, and optional parity
bits. Finally, it outputs a composite serial data stream on the channel transmitter serial data output signal
(SOUT). The transmitter status may be polled or interrupt driven.
The receiver accepts serial data bits on the channel receiver serial data input signal (SIN), converts it to
parallel format, checks for a start bit, parity (if any), stop bits, and transfers the assembled character (with
start, stop, parity bits removed) from the receiver buffer (or FIFO) in response to a read of the UART’s
receiver buffer register (URBR). The receiver status may be polled or interrupt driven.
12-2
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Clear to send (CTS) and ready to send (RTS) modem control functions
Software-selectable serial interface data format (data length, parity, 1/1.5/2 STOP bit, baud rate)
Line and modem status registers
Line-break detection and generation
Internal diagnostic support, local loopback, and break functions
Prioritized interrupt reporting
Overrun, parity, and framing error detection
Address Bus
Modes of Operation
Data
Control
int
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
platform clock
HRESET
Interrupt
Control
Control
Logic
Figure 12-1. UART Block Diagram
Baud Rate Generator
Transmit Buffer
Receive Buffer
16-Bit Counter/
Output Port
Input Port
Freescale Semiconductor
SIN
SOUT
CTS
RTS