MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 520

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.2.3
The AFEU context/data size register (shown in
data to be processed by the AFEU.
In channel-driven access, the necessary writes to this register are performed automatically, based on
information contained in the descriptors.
In host-driven access, the correct order of operations for an AFEU operation with context loading is as
follows:
This register is cleared when the AFEU is reset or re-initialized, shown in
10-90
Offset 0x3_8008
Reset
1. Write the AFEU mode register, with 'Context Source' and 'Prevent Permute' set.
2. Write the 259 bytes of previously saved S-Box (256 bytes) and counters (3 bytes) to the AFEU
3. Write 2072 (bits) to the AFEU context/data size register
4. Begin writing the data to the AFEU Input FIFO. If the total data size is > 256 bytes, monitor the
5. After writing the final data to the Input FIFO, write the data size (in bits) to the AFEU context/data
W
R
0
input FIFO.
input FIFO level (IFL) in the AFEU Status Register to avoid overflowing the Input FIFO. Use the
Output FIFO Level (OFL) to avoid underflowing the Output FIFO.
size register. The data size written must be an integral number of bytes (bits 61:63 must be zero) or
the AFEU will generate a data size error. The AFEU performs additional checking on bits 57:60
to determine the number of bytes of data from the final Input FIFO write to permute with the
S-Box.
AFEU Context/Data Size Register
The device driver must create properly formatted descriptors for situations
requiring a key permute prior to ciphering. When using host-controlled
access (typically for debug), the user must set the AFEU mode register to
perform ‘permute with key’, then write the key data to AFEU Key Registers,
then write the key size to the key size register. The AFEU starts permuting
the memory with the contents of the key registers immediately after the key
size is written.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 10-33. AFEU Key Size Register
—
Figure
NOTE
All zeros
20-64), specifies the number of bits of context or
Figure
51 52
10-34.
Freescale Semiconductor
Access: Read/Write
Key Size
63