MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1005

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 15-15
15.3.1.10
The current list descriptor address registers, shown in
address of the list descriptor in memory in extended chaining mode.
In extended chaining mode, software must initialize CLSDARn and ECLSDARn to point to the first list
descriptor in memory. After finishing the last link descriptor in the current list, the DMA controller loads
the contents of the next list descriptor address register into the current list descriptor address register. If
NLSDARn[EOLSD] in the next list descriptor address register is clear, the DMA controller reads the new
current list descriptor from memory to process that list. If EOLSD in the next list descriptor address
register is set and the last link in the current list is finished all DMA transfers are complete.
Freescale Semiconductor
29–30
Offset 0x124
Bits
Reset
28
31
W
R
28–31
0–27
Bit
0x1A4
0x224
0x2A4
0
NDEOSIE Next descriptor end-of-segment interrupt enable
EOLND
Name
—
describes the fields of the ENLNDARn registers.
Current List Descriptor Address Registers (CLSDAR n and ECLSDAR n )
Figure 15-15. Extended Next Link Descriptor Address Registers (ENLNDAR n )
ENLNDA
Name
0 Do not generate an interrupt if the current DMA transfer for the current descriptor is finished.
1 Generate an interrupt if the current DMA transfer for the current descriptor is finished.
Reserved
End-of-links descriptor. This bit is ignored in direct mode.
0 This descriptor is not the last link descriptor in memory for this list.
1 This descriptor is the last link descriptor in memory for this list. If this bit is set, the DMA controller
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
advances to the next list descriptor in memory if NLSDAR n [EOLSD] is also set in extended mode.
Table 15-14. NLNDAR n Field Descriptions (continued)
Reserved
Next link descriptor extended address bits (upper 4 bits of 36-bit address)
Table 15-15. ENLNDAR n Field Descriptions
—
All zeros
Figure 15-17
Description
Description
and
Table
15-17, contain the current
Access: Read/Write
27 28
DMA Controller
ENLNDA
15-19
31