MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1356

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
bandwidth and power on the system bus and thus should be minimized (not necessarily eliminated).
Back-offs can be minimized with use of the TSCHHEALTH (T
21-22
Offset 0x164
Reset 0
31–22
21–16
15–13
12–8
Bits
7–0
W
R
31
TXSCHHEALTH Scheduler health counter. Increment when the host controller fails to fill the TX latency FIFO to the
TXFIFOTHRES FIFO burst threshold. Control the number of data bursts that are posted to the TX latency FIFO in
0
TXSCHOH
Name
0
—
—
0
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Figure 21-17. Transmit FIFO Tuning Controls (TXFILLTUNING)
0
Reserved, should be cleared.
host mode before the packet begins on to the bus. The minimum value is 2 and this value should be
a low as possible to maximize USB performance. A higher value can be used in systems with
unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data
transferred from the latency FIFO to USB occurs before it can be replenished from system memory.
This value is ignored if USBMODE[SDIS] (stream disable bit) is set. When USBMODE[SDIS] is set,
the host controller behaves as if TXFIFOTHRES is set to the maximum value.
Reserved, should be cleared.
level programmed by TXFIFOTHRES before running out of time to send the packet before the next
Start-Of-Frame.
This health counter measures the number of times this occurs to provide feedback to selecting a
proper TXSCHOH. Writing to this register clears the counter and this counter stops counting after
reaching the maximum of 31.
Scheduler overhead. These bits add an additional fixed offset to the schedule time estimator
described above as T
number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly
utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly
reduce USB utilization.
The time unit represented in this register is 1.267 s when a device is connected in high-speed
mode.
The time unit represented in this register is 6.333 s when a device is connected in low-/full-speed
mode.
For most applications, TXSCHOH can be set to 4 or less. A good value to begin with is:
TXFIFOTHRES
higher integer. TimeUnit is either 1.267 or 6.333 as noted earlier in this description. For example, if
TXFIFOTHRES is 5 and BURSTSIZE is 8, then set TXSCHOH to 5 (8 4) (40 1.267)=4 for a
high-speed link. If this value of TXSCHOH results in a TXSCHHEALTH count of 0 per second, try
lowering the value by 1 if optimizing performance is desired. If TXSCHHEALTH exceeds 10 per
second, try raising the value by 1.
If streaming mode is disabled via the USBMODE register, treat TXFIFOTHRES as the maximum
value for purposes of the TXSCHOH calculation.
Table 21-19. TXFILLTUNING Register Field Descriptions
0
0
0
22 21
0
0
(BURSTSIZE
TXFIFOTHRES
0
ff
. As an approximation, the value chosen for this register should limit the
0
0
1
4 bytes-per-word)
16 15
0
0
Description
—
0
13 12
0
ff
) parameter described below.
TXSCHHEALTH
0
(40
0
0
TimeUnit ), always rounded to the next
0
8
0
7
0
Freescale Semiconductor
0
0
Access: Read/Write
TXSCHOH
0
0
0
0
0
0