MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1527

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.4.1.28 SerDes1 Control Register 0 (SRDS1CR0)
Shown in
Freescale Semiconductor
Offset 0xE_3000
Reset
Reset
12–20
22–31
Bits
21
W
W
R
R
—
16
0
0
Figure
0
DEEPSLEEP_Z
Name
17
0
1
—
—
1
23-28, SRDS1CR0 contains functional control bits for the SerDes1 logic.
TXEQAD
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
0
2
19
3
1
0
Figure 23-28. SerDes1 Control Register 0 (SRDS1CR0)
Reserved
Deep sleep pad disable
0 Normal operation. In deep sleep all input and output pads remain driven as per normal
1 When in deep sleep mode, output pads that are not used for wakeup events are tristated,
Reserved
• Dual eTSEC (including Ethernet management interface and GbE clocking but not 1588)
• Triple USB
• GPIO
• DDR
• Interrupts (IRQ[0:11], MCP, UDE, IRQ_OUT)
• System control (HRESET, HRESET_REQ, SRESET, CKSTP_IN, CKSTP_OUT)
• Debug (TRIG_IN, TRIG_OUT, MSRCID[0:4], MDVAL, CLK_OUT)
• Power management (ASLEEP, POWER_EN, POWER_OK)
• Clocking (SYSCLK, RTC, DDRCLK)
• DFT (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, TEST_SEL)
Table 23-30. GCR Field Descriptions (continued)
functional operation, and inputs remain enabled.
and the receivers of pad inputs are disabled. When waking from Deep sleep, pad inputs are
re-enabled as soon as the wakeup event occurs, but pad outputs are un-tristated only after
the reset counter PMRCCR[RCNT] expires. This affects all digital I/O pins except the
following:
—
20
0
0
4
21
0
1
5
TXEQEH
0
0
6
23
1
0
7
SDPD
24
0
0
8
—
25
0
0
Description
26
0
1
11
27
0
1
12
28
0
0
—
13
29
0
0
Access: Read/Write
14
30
0
0
Global Utilities
23-35
15
31
0
0