MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 412

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10–11
12–15 PRIORITY Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level of
16–31 VECTOR Vector (Affects only interrupts routed to int ). Contains the value returned when IACK is read and this interrupt
Programmable Interrupt Controller (PIC)
9.3.7.2
The EIDRs, shown in
any of IRQ[]. Only one destination bit may be set; otherwise, behavior is undefined.
Offset EIDR0: 0x0010; IDR1: 0x0030; EIDR2: 0x0050; EIDR3: 0x0070; EIDR4:
Table 9-39
9-42
Reset 0
Bits
Bits Name
2–7
8
9
0
1
W
R
0x0090; EIDR5: 0x00B0; EIDR6: 0x00D0; EIDR7: 0x00F0; EIDR8: 0x0110;
EIDR9: 0x0130; EIDR10: 0x0150; EIDR11: 0x0170
1
EP CI0 CI1
CI0
0
EP
Name
Reserved in single-processor implementations.
—
—
P
S
1
0
describes the EIDR fields.
External signal. Allows interrupt to be serviced externally. EP should be set only for level-sensitive external
interrupts (EIVPR n [S]= 1). Setting for edge-sensitive does not provide reliable interrupt response.
0 Interrupt is not routed to IRQ_OUT.
1 Interrupt is routed to IRQ_OUT for external service.
Critical interrupt 0. Ci n fields should be set only for level-sensitive external interrupts (EIVPR n [S]= 1). Setting them
for edge-sensitive does not provide reliable interrupt response.
0 Processor core 0 does not receive this interrupt.
1 Directs the external interrupt to processor core 0 by causing the cint0 output signal from the PIC to assert. See
External Interrupt Destination Registers (EIDR0–EIDR11)
Section 9.1.2, “Interrupts to the Processor Core.”
0
2
Reserved, should be cleared.
Polarity. Specifies the polarity for the external interrupt.
0 Polarity is active-low or negative edge-triggered.
1 Polarity is active-high or positive edge-triggered.
Sense. Specifies the sense for external interrupts.
0 The external interrupt is edge sensitive.
1 The external interrupt is level sensitive. This setting must be used to direct the interrupt to IRQ_OUT or cint .
Note: If an IRQ n signal is used to receive INT x signals from one of the PCI Express ports as a root complex,
S must be set to be level-sensitive.
Reserved, should be cleared.
0 inhibits signalling of this interrupt to the core. Affects only interrupts routed to int .
resides in the corresponding interrupt request register (IRR) for that core, as shown in
1
3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure
Figure 9-39. External Interrupt Destination Registers (EIDRs)
Table 9-38. EIVPR n Field Descriptions (continued)
9-39, control the destination of external interrupts caused by the assertion of
Table 9-39. EIDR n Field Descriptions
Description
Description
—
Freescale Semiconductor
Figure
Access: Read/Write
9-50.
29
0
P1
30
0
1
P0
31
1