MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 761

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
TSEC_1588_CLK
TSEC n _TXD[7:0]
TSEC n _TX_EN
TSEC n _TX_ER
PULSE_OUT1
PULSE_OUT2
TSEC_1588_
TSEC_1588_
TSEC_1588_
TSEC_1588_
TSEC_1588_
CLK_OUT
TRIG_IN0
TRIG_IN1
Signal
Table 14-2. eTSEC Signals—Detailed Signal Descriptions (continued)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
I/O
O
O
O
O
O
O
I
I
i
Transmit data out. In GMII mode, TSEC n _TXD[7:0] represents one complete octet of data to be
sent from the MAC to the PHY when TSEC_TX_DV is asserted and has no meaning while
TSEC n _TX_EN is negated.
In TBI mode, TSEC n _TXD[7:4] represents transmit code group (TCG) bits 7:4. Together, with
TCG[9:8] and TCG[3:0], they represent the 10-bit encoded symbol.
In GMII or MII mode, TSEC n _TXD[3:0] represent a nibble of data to be sent from the MAC to the
PHY when TSEC n _TX_EN is asserted and have no meaning while TSEC n _TX_EN is negated.
In RGMII or RTBI mode, data bits 3:0 are transmitted on the rising edge of TSEC n _TX_CLK, and
data bits 7:4 are transmitted on the falling edge of TSEC n _TX_CLK.
In TBI mode, TSEC n _TXD[3:0] represents TCG[3:0]. Together, with TCG[9:4], they represent the
10-bit encoded symbol.
In RMII mode, TSEC n _TXD[1:0] represents TXD[1:0], which is valid data sent to the PHY when
TSEC n _TX_EN is asserted, or undefined otherwise.
In FIFO mode, TSEC n _TXD[7:4] with TSEC n _TXD[3:0] represent one complete octet of data to
be received from the external FIFO device.
Note that some of these signals are also used during reset to configure the eTSEC interface
mode.
Transmit data valid. In GMII, MII, or RMII mode, if TSEC n _TX_EN is asserted, the MAC is
indicating that valid data is present on the GMII’s or the MII’s TSEC n _TXD signals.
In RGMII mode, TSEC n _TX_EN becomes TX_CTL. TX_EN and TX_ERR are asserted on this
signal on rising and falling edges of the TSEC n _GTX_CLK, respectively.
In TBI mode, TSEC n _TX_EN represents TCG[8]. Together, with TCG[9] and TCG[7:0], they
represent the 10-bit encoded symbol.
In RTBI mode, TSEC n _TX_EN represents TCG[4] on the rising edge and TCG[9] on the falling
edge of TSEC n _GTX_CLK, respectively. Together with TCG[3:0] and TCG[8:5], they represent
the 10-bit encoded symbol.
In FIFO mode TSEC n _TX_EN is used to indicate valid data (GMII-style protocols) or forms part
of the transmit control flags (encoded packet protocols).
Transmit error. In GMII or MII mode, assertion of TSEC n _TX_ER for one or more clock cycles
while TSEC n _TX_EN is asserted causes the PHY to transmit one or more illegal symbols.
Asserting TSEC n _TX_ER has no effect while operating at 10 Mbps or while TSEC n _TX_EN is
negated. This signal transitions synchronously with respect to TSEC n _TX_CLK.
In TBI mode, TSEC n _TX_ER represents TCG[9]. Together, with TCG[8:0], they represents the
10-bit encoded symbol.
In FIFO mode TSEC n _TX_ER represents either transmit data error (GMII-style protocols) or
forms part of the transmit control flags (encoded packet protocols).
This signal is not used in the eTSEC RMII, RTBI, or RGMII modes and is driven low.
1588 clock out. Phase aligned timer clock divider output (chip external output pin).
1588 trigger in 0. External timer trigger input 0.This is an asynchronous general purpose input
(chip external input pin).
1588 trigger in 1. External timer trigger input 1.This is an asynchronous general purpose input
(chip external input pin).
1588 pulse out 1. Timer pulse per period 1. It is phase aligned with 1588 timer clock (chip external
output pin)
1588 pulse out 2. Timer pulse per period 2. It is phase aligned with 1588 timer clock (chip external
output pin)
1588 clock in. External high precision timer reference clock input (chip external input pin).
Description
Enhanced Three-Speed Ethernet Controllers
14-13