MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1138

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.3.6.8
Together with the other PCI Express error capture registers, PEX_ERR_CAP_R3 allows vital error
information to be captured when an error occurs. Different error information is reported depending on
whether the error source is from an outbound transaction from an internal source or from an inbound
transaction from an external source; the source of the captured error is reflected in
PEX_ERR_CAP_STAT[GSID]. Note that after the initial error is captured, no further capturing is
performed until the PEX_ERR_CAP_STAT[ECV] bit is clear.
17.3.6.8.1
PEX_ERR_CAP_R3 for the case when the error is caused by an outbound transaction from an internal
source (that is, PEX_ERR_CAP_STAT[GSID]
Table 17-35
outbound transaction from an internal source.
17.3.6.8.2
PEX_ERR_CAP_R3 for the case when the error is caused by an inbound transaction from an external
source (that is, PEX_ERR_CAP_STAT[GSID] = 0h02 for controller 1), is shown in
Table 17-36
in PEX_ERR_CAP_R0 (see
transaction. Note that PEX_ERR_CAP_R3 captures the lower half of the 64-bit address for a 4 DW
17-42
Offset 0xE34
Reset
Offset 0xE34
Reset
W
W
R
R
0
0
0–31
Bits
describes the fields of PEX_ERR_CAP_R3 for the case when the FMT and TYPE subfields
describes the fields of PEX_ERR_CAP_R3 for the case when the error is caused by an
PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)
PEX_ERR_CAP_R3—Outbound Case
PEX_ERR_CAP_R3—Inbound Case
Figure 17-34. PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)
Figure 17-35. PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)
Table 17-35. PCI Express Error Capture Register 3 Field Descriptions
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Name
OD2
Internal platform transaction information. Reserved for factory debug.
Table
Internal Source, Outbound Transaction
Internal Source, Outbound Transaction
External Source, Inbound Transaction
17-28) indicate the error was caused by an inbound memory request
0h02), is shown in
All zeros
All zeros
OD2
GH3
Description
Figure
17-34.
Freescale Semiconductor
Figure
Access: Read/Write
Access: Read/Write
17-35.
31
31