MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 423

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

request register (IRR). The source’s vector (xVPRn[VECTOR]) is copied to IACK[VECTOR], which the
interrupt handler retrieves by reading IACK.
If the priority (xVPRn[PRIORITY]) of an interrupt latched in the IRR is higher than the value in the target
processor’s CTPR[TASKP], the interrupt router asserts the external interrupt signal (int), causing that
processor core to vector to its external interrupt handler.
The interrupt handler must acknowledge the interrupt by explicitly reading the corresponding IACK
register, described in
(IACK0–IACK1).” The PIC interprets this read as an interrupt acknowledge (IACK) cycle. The IACK
cycle not only returns the source’s vector, it also negates the int signal to the processor (making it possible
for a higher priority interrupt to assert int) and sets the source’s bit in the ISR, indicating that this interrupt
Freescale Semiconductor
1
2
3
programmable through
If cint or IRQ_OUT is the destination, EIVPR n [S] must be set to configure the source as level sensitive.
If multiple destination register bits are set, PIC behavior is undefined.
Although setting CI n directs the interrupt request to the critical interrupt output ( cint0 / cint1 ), integrated logic may
connect this signal to a different interrupt input to the core.
x VPR n [PRIORITY]
PIC Configuration
x VPR n [VECTOR]
Status Registers
IACK[VECTOR]
(defined by the
CTPR[TASKP]
specification)
x VPR n [MSK]
Interrupt sources
OpenPIC
x VPR n [A]
the PIC
Figure 9-50. PIC Interrupt Processing Flow Diagram for Each Core ( n )
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 9.3.8.4, “Processor Core Interrupt Acknowledge Registers 0–1
x VPR n [PRIORITY]
Interrupt Service Routine
Read IACK / Retrieves vector (IACK[VECTOR]), negates int,
Set MSR[EE]/ Enables recognition of int for higher priority interrupt
. . .
Write EOI / Clears ISR bit to remove interrupt from service
rfi
Interprocessor
Global Timer
CTPR[TASKP]
greater than
interrupt pending register (IPR )
int0 (if x IDR n [P0] = 1)
int1 (if x IDR n [P1] = 1)
/ puts interrupt in service (sets ISR bit)
/ Returns control to and restores state of interrupted process
If true
mask register
Destination:
If true
Message Signaled
interrupt request register (IRR)
Message
External
Internal
Interrupt Selector
Interrupt Router
2
int0 (if x VPR n [P0] = 1)
int1 (if x VPR n [P1] = 1)
Core
Level sensitive only
in-service register (ISR)
x IDR n [CI n ] = 1
x IDR n [EP] = 1
Highest priority interrupt in IPR (non
masked) and ISR is chosen.
If x VPR n [PRIORITY] > CTPR[TASKP], int is
asserted and x VPR n [VECTOR] is copied to
IACK[VECTOR]
Programmable Interrupt Controller (PIC)
2
cint0 (if x IDR n [CI0] = 1)
cint1 (if x IDR n [CI1] = 1)
IRQ_OUT
Interrupt Output
3
9-53