MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 83

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table
Number
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
8-18
8-19
8-20
8-21
Freescale Semiconductor
L2ERRADDRH Field Description ....................................................................................... 6-25
L2ERRCTL Field Descriptions ............................................................................................ 6-25
Fastest Read Timing—Hit in L2 ........................................................................................... 6-27
PLRU Bit Update Algorithm ................................................................................................ 6-32
PLRU-Based Victim Selection Mechanism .......................................................................... 6-33
L2 Cache States..................................................................................................................... 6-35
State Transitions Due to Core-Initiated Transactions ........................................................... 6-35
State Transitions Due to System-Initiated Transactions ....................................................... 6-38
L2 Cache ECC Syndrome Encoding..................................................................................... 6-39
L2 Cache ECC Syndrome Encoding (Check Bits) ............................................................... 6-40
ECM Memory Map ................................................................................................................. 7-3
EEBACR Field Descriptions .................................................................................................. 7-4
EEBPCR Field Descriptions ................................................................................................... 7-4
EIPBRR1 Field Descriptions .................................................................................................. 7-5
EIPBRR2 Field Descriptions .................................................................................................. 7-6
EEDR Field Descriptions........................................................................................................ 7-6
EEER Field Descriptions ........................................................................................................ 7-7
EEATR Field Descriptions...................................................................................................... 7-7
EELADR Field Descriptions .................................................................................................. 7-8
EEHADR Field Descriptions .................................................................................................. 7-9
DDR Memory Interface Signal Summary .............................................................................. 8-4
Memory Address Signal Mappings......................................................................................... 8-5
Memory Interface Signals—Detailed Signal Descriptions ..................................................... 8-6
Clock Signals—Detailed Signal Descriptions ...................................................................... 8-10
DDR Memory Controller Memory Map............................................................................... 8-10
CSn_BNDS Field Descriptions............................................................................................. 8-13
CSn_CONFIG Field Descriptions ........................................................................................ 8-14
CSn_CONFIG_2 Field Descriptions .................................................................................... 8-15
TIMING_CFG_3 Field Descriptions .................................................................................... 8-16
TIMING_CFG_0 Field Descriptions .................................................................................... 8-18
TIMING_CFG_1 Field Descriptions .................................................................................... 8-20
TIMING_CFG_2 Field Descriptions .................................................................................... 8-22
DDR_SDRAM_CFG Field Descriptions.............................................................................. 8-24
DDR_SDRAM_CFG_2 Field Descriptions.......................................................................... 8-27
DDR_SDRAM_MODE Field Descriptions.......................................................................... 8-29
DDR_SDRAM_MODE_2 Field Descriptions...................................................................... 8-30
DDR_SDRAM_MD_CNTL Field Descriptions................................................................... 8-31
Settings of DDR_SDRAM_MD_CNTL Fields .................................................................... 8-32
DDR_SDRAM_INTERVAL Field Descriptions .................................................................. 8-33
DDR_DATA_INIT Field Descriptions ................................................................................. 8-33
DDR_SDRAM_CLK_CNTL Field Descriptions ................................................................. 8-34
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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