MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1350

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21-16
Offset 0x148
Reset
Reset
31–11
Bits
10
9
8
7
6
5
4
3
W
W
R
R
31
15
ULPIE
Name
SRE
URE
AAE
SEE
FRE
SLE
—
—
Reserved, should be cleared.
ULPI interrupt enable. An event completion to the viewport register sets the USBSTS[ULPII]. If the ULPI
enables ULPIE bit to be set, then the USBINT (USBSTS[UI]) will occur.
0 Disable
1 Enable
Reserved, should be cleared.
Sleep enable. This is a non-EHCI bit. When this bit is a one, and USBSTS[SLI] transitions, the USB
controller will issue an interrupt. The interrupt is acknowledged by software writing a one to USBSTS[SLI].
Only used in device mode.
0 Disable
1 Enable
SOF received enable. This is a non-EHCI bit. When this bit is a one, and USBSTS[SRI] is a one, the
controller will issue an interrupt. The interrupt is acknowledged by software clearing USBSTS[SRI].
0 Disable
1 Enable
USB reset enable. This is a non-EHCI bit. When this bit is a one, USBSTS[URI] is a one, the device
controller will issue an interrupt. The interrupt is acknowledged by software clearing USBSTS[URI] bit. Only
used in device mode.
0 Disable
1 Enable
Interrupt on async advance enable. When this bit is a one, and USBSTS[AAI] is a one, the controller will
issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing
USBSTS[AAI]. Only used in host mode.
0 Disable
1 Enable
System error enable. When this bit is a one, and USBSTS[SEI] is a one, the controller will issue an interrupt.
The interrupt is acknowledged by software clearing USBSTS[SEI].
0 Disable
1 Enable
Frame list rollover enable. When this bit is a one, and USBSTS[FRI] is a one, the controller will issue an
interrupt. The interrupt is acknowledged by software clearing USBSTS[FRI]. Only used by the host mode.
0 Disable
1 Enable
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Table 21-11. USBINTR Register Field Descriptions
Figure 21-10. USB Interrupt Enable (USBINTR)
11
ULPIE
10
—
9
SLE
All zeros
All zeros
8
—
Description
SRE
7
URE
6
AAE
5
SEE
4
FRE
3
Freescale Semiconductor
PCE
Access: Read/Write
2
UEE
1
UE
16
0