MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1217

Manufacturer Part Number

BOARD DEV SYSTEM MPC8536E

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Board, Software and Documentation

Processor Series

Data Bus Width

Maximum Clock Frequency

Operating Supply Voltage

- 0.3 V to + 1.21 V

Maximum Operating Temperature

Data Ram Size

Interface Type

Program Memory Type

DDR2, DDR3, SDRAM

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

0.95V To 1.05V

Rohs Compliant

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The eSPI can be programmed to work in a single master environment. This section describes eSPI master

operation in a single-master configuration.

In master mode, the eSPI sends a message to the slave peripheral, which sends back a simultaneous reply.

A single master with multiple slaves uses up to 4 chip select signals to selectively enable slaves, as shown

To start exchanging data, the core writes the data to be sent into the SPITF register. The eSPI then generates

programmable clock pulses on SPI_CLK for each character. It shifts Tx data out on the “eSPI master-out

slave-in” (SPI_MOSI) and Rx data in on the eSPI “master-in slave-out” (SPI_MISO) simultaneously.

During the transmission process the core is responsible for supplying the data whenever the eSPI requests

it to ensure smooth operation.

The maximum sustained data rate that the eSPI supports depends on the SW latency. However, the eSPI

can transfer a single character at very high rates— system clock/2 up to a maximum specified by the device

hardware specifications. Gaps might be inserted between multiple frames.

The eSPI interface consists of transmit, receive, clock and chip selects

Freescale Semiconductor

External Signal Descriptions

Modes of Operation

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Figure 18-2. Single-Master/Multi-Slave Configuration

Enhanced Serial Peripheral Interface