MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 819

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.3.3.14 Receive Stamp Register (TMR_RXTS_H/L)
Receive time stamp register (RXTS_H/L). This register holds the value present in TMR_CNT_H/L when
the eTSEC detects a new incoming Ethernet frame. This register is only updated when the precision time
stamp logic is enable via TMR_CTRL[TE]. This register is read only in normal operation. Figure 14-38
describes the definition for the RXTS_H/L register.
Offset eTSEC1:0x2_44C4;
Table 14-42
14.5.3.4
This section describes the MAC registers and provides a brief overview of the functionality that can be
exercised through the use of these registers, particularly those that provide functionality not explicitly
required by the IEEE 802.3 standard. All of the MAC registers are 32 bits wide.
14.5.3.4.1
The MAC configuration registers 1 and 2 provide for configuring the MAC in multiple ways:
14.5.3.4.2
The half-duplex register (HAFDUP) allows control over the carrier-sense multiple access/collision
detection (CSMA/CD) logic of the eTSEC. Half-duplex mode is only supported for 10- and 100-Mbps
operation. Following the completion of the packet transmission the part begins timing the inter packet gap
(IPG) as programmed in the back-to-back IPG configuration register. The system is now free to begin
another frame transfer.
Freescale Semiconductor
Reset
0–63 TMR_RXTS_H/L Value of the eTSEC precision timer upon detection of a start of frame symbol for the received frame.
Bits
W
R
•
•
eTSEC3:0x2_64C4
0
Adjusting the preamble length—The length of the preamble can be adjusted from the nominal
seven bytes to some other (non-zero) value. Should custom preamble insertion/extraction be
configured, then this register must by left at its default value.
Varying pad/CRC combinations—Three different pad/CRC combinations are provided to handle a
variety of system requirements. Simplest are frames that already have a valid frame check
sequence (FCS) field. The other two options include appending a valid CRC or padding and then
appending a valid CRC, resulting in a minimum frame of 64 octets. In addition to the
programmable register set, the pad/CRC behavior can be dynamically adjusted on a per-packet
basis.
Name
describes the fields of the TMR_RXTS_H/L register.
MAC Functionality
Configuring the MAC
Controlling CSMA/CD
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
TMR_RXTS_H
Table 14-42. TMR_RXTS_H/L Register Field Descriptions
Figure 14-38. TMR_RXTS_H/L Register Definition
All zeros
31 32
Description
Enhanced Three-Speed Ethernet Controllers
TMR_RXTS_L
Access: Read/Write
14-71
63