MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1497

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.4.1
This section describes the global utilities registers in detail.
23.4.1.1
PORPLLSR, shown in
cfg_core_pll[0:1], and cfg_pci_clk POR configuration pins. See
Section 4.4.3.2, “e500 Core PLL Ratio,”
Freescale Semiconductor
0xE_310C SRDS2CR3—SerDes2 control register 3
0xE_3000 SRDS1CR0—SerDes1 control register 0
0xE_3008 SRDS1CR2—SerDes1 control register 2
0xE_3100 SRDS2CR0—SerDes2 control register 0
0xE_3104 SRDS2CR1—SerDes2 control register 1
0xE_3108 SRDS2CR2—SerDes2 control register 2
Offset
0xB28
0xE00
0xE20
0xE60
Offset 0x000
Reset
Reset
W
W
R
R PCI_clk_sel
DDRCLKDR—DDR clock disable register
CLKOCR—Clock out control register
ECMCR—ECM control register
GCR—General control register
Register Descriptions
POR PLL Status Register (PORPLLSR)
16
0
n
0
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 23-3. Global Utilities Module Memory Map (continued)
Figure
17
0
0
1
Figure 23-1. POR PLL Status Register (PORPLLSR)
SerDes1 Registers—Block Base Address 0xE_3000
SerDes2 Registers—Block Base Address 0xE_3100
23-1, contains the settings for the PLL ratios as set by the cfg_sys_pll[0:3],
2
n
0
Register
n
0
DDR_Ratio
n
0
for more information.
Debug Control Registers
n
0
—
n
0
6
—
0
n
7
0
1
Section 4.4.3.1, “System PLL
Access
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
25
1
1
0x0000_1C1C
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_ n 000
0x1100_4430
0x0000_0040
0x1100_4430
0x0000_0040
0x0101_0000
10
26
n
n
Reset
n
n
Plat_Ratio
e500_Ratio
n
n
Access: Read only
23.4.1.28/2323-35
23.4.1.29/2323-37
23.4.1.30/2323-39
23.4.1.31/2323-41
23.4.1.32/2323-42
23.4.1.33/2323-44
n
n
23.4.1.24/23-32
23.4.1.25/23-33
23.4.1.26/23-33
23.4.1.27/23-34
Section/page
Ratio,” and
Global Utilities
30
n
n
15
31
n
0
n
23-5