MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 690

Manufacturer Part Number

BOARD DEV SYSTEM MPC8536E

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Board, Software and Documentation

Processor Series

Data Bus Width

Maximum Clock Frequency

Operating Supply Voltage

- 0.3 V to + 1.21 V

Maximum Operating Temperature

Data Ram Size

Interface Type

Program Memory Type

DDR2, DDR3, SDRAM

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

0.95V To 1.05V

Rohs Compliant

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Enhanced Local Bus Controller

edges of LCLK, but continues to sample synchronous read data on rising edges of LCLK to maximize the

set-up margin for reads.

The GPCM allows a minimal glue logic and flexible interface to SRAM, EPROM, FEPROM, ROM

devices, and external peripherals. The GPCM contains two basic configuration register groups—BRn and

Figure 13-34

mode. Byte-write enable signals (LWE) are available for each byte written to memory. Also, the output

enable signal (LOE) is provided to minimize external glue logic. On system reset, a global (boot)

chip-select is available that provides a boot ROM chip-select (LCS0) prior to the system being fully

General-Purpose Chip-Select Machine (GPCM)

shows a simple connection between an 8-bit port size SRAM device and the eLBC in GPCM

Figure 13-33. eLBC Bus Cycles in PLL-bypassed Mode (GPCM and UPM only)

Since LCLK is not used for NAND Flash EEPROMs controlled by FCM,

the eLBC drives and samples data on the same edge (rising edge when

LCRR[PBYP] = 0 and falling edge when LCRR[PBYP] = 1) on FCM

controlled banks.

Figure 13-32. eLBC Bus Cycles in PLL Mode (GPCM and UPM only)

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Freescale Semiconductor